Improved Low-Power,

CMOS Analog Switches with Latches

_______________________________________________________________________________________

9

_____________________________________________Pin Configurations (continued)

21

20

D3

S3

N.C.

S4

D4

18

17

16

15

14

4

5

6

7

8

V-

GND

N.C.

V+

319

13

910

11

12

DG423

DG425

PLCC

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

S1

IN1

V-

GND

S3

D3

WR

D1

DG423

DG425

V+

IN2

S2

D2

RS

D4

S4

DIP

_____________________________Functional Diagrams/Truth Tables (continued)

WR

RS

IN

SWITCH 1, 2

0

1

0

1

Off

On

LOGIC "O"

≤ 0.8V

LOGIC "1"

≥ 2.4V

DG423 TRUTH TABLE

D2

D1

CK

D

Q

TWO SPDT SWITCHES PER PACKAGE

S1

WR

IN1

IN2

RS

S2

DG423

S3

R

Q

CK

D

Q

R Q

S4

D3

D4

SWITCH 3, 4

On

Off

D2

D1

CK

D

TWO DPST SWITCHES PER PACKAGE

S1

WR

IN1

IN2

RS

S2

DG425

S3

R

Q

CK

D

R Q

S4

D3

D4

WR RS IN SWITCH

01

0

1

Off

On

LOGIC "O"

≤ 0.8V

LOGIC "1"

≥ 2.4V

DG425 TRUTH TABLE

LATCH OPERATION TRUTH TABLE

WR

RS

IN

X1

X1

LATCH/SWITCH X

X

X

0

0

X

X

Latch operation transparent.

Control data latched in.

Switches on or off as selected by last IN.

All latches reset. Switches on or off as

when IN = 0, WR = 0, RS = 1.

TOP VIEW

N.C. = No Internal Connection