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DG421C/D Datasheet(PDF) 6 Page - Maxim Integrated Products |
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DG421C/D Datasheet(HTML) 6 Page - Maxim Integrated Products |
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6 / 12 page ![]() Improved Low-Power, CMOS Analog Switches with Latches 6 _______________________________________________________________________________________ D -15V ( ) V- RL VOUT V+ +15V +5V VL GND VD = 10V for tON VD = -10V for tOFF IN LOGIC INPUT REPEAT TEST FOR IN2 AND S2. CL INCLUDES FIXTURE AND STRAY CAPACITANCE. CL SWITCH OUTPUT S LOGIC INPUT SWITCH OUTPUT tR < 20ns tF < 20ns VOUT tOFF 50% 3V 0V 0V NOTE: LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. DG421 DG423 DG425 VOUT = VD RL RL + rDS(ON) 0.9 x VOUT 0.9 x VOUT -VOUT tON *VD = 10V for tON, VD = -10V for tOFF Figure 2. Switching Time 3V 0 3V 0 3V 0 VOUT 0 WR IN RS SWITCH OUTPUT 1.5V tWW tDW tWD 2.0V 0.8V 1.5V tRS tOFF(RS) 0.8 x VOUT Figure 3. Latch Timing VOUT is the steady-state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. ______________________________________________Timing Diagrams/Test Circuits |
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