250Msps, 8-Bit ADC with Track/Hold

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13

Reference

The ADC’s reference resistor is a Kelvin-sensed, center-

tapped resistor string that sets the ADC’s LSB size and

dynamic operating range. Normally, the top and bottom of

this string are driven with an op amp, and the center tap is

left open. However, driving the center tap is an effective

way to modify the output coding to provide a user-defined

bilinear response. The buffer amplifier used to drive the

top and bottom inputs will need to supply approximately

18mA due to the resistor string impedance of 116

Ω mini-

mum. A reference voltage of ±1.02V is normally applied to

adjusted up to ±1.4V to accommodate extended input

requirements (accuracy specifications are guaranteed with

to increase precision.

An RC network at the ADC’s reference terminals is

needed for best performance. This network consists of

a 33

Ω resistor connected in series with the op amp out-

put that drives the reference. A 0.47µF capacitor must

be connected near the resistor at the op amp’s output

(see

Typical Operating Circuit). This resistor and

capacitor combination should be located within 0.5

inches of the MAX100 package. Any noise on these

pins will directly affect the code uncertainty and

degrade the ADC’s effective-bits performance.

CLK and DCLK

All input and output clock signals are differential. The

input clocks, CLK and CLK, are the primary timing sig-

nals for the MAX100. CLK and CLK are fed to the inter-

nal circuitry from pins 2 & 3 or pins 62 & 61 through an

internal 50

Ω transmission line. One pair of CLK/CLK

inputs should be driven and the other pair terminated

by 50

Ω to -2V. Either pair can be used as the driven

inputs (input lines are balanced) for easy circuit con-

CLK and CLK (Figures 1–4).

For best performance and consistent results, use a low

phase-jitter clock source for CLK and CLK. Phase jitter

larger than 2ps from the input clock source reduces the

converter’s effective-bits performance and causes

inconsistent results.

DCLK and DCLK are output clock signals derived from

the input clocks and are used for external timing of the

AData and BData outputs. The MAX100 is character-

ized to work with maximum input clock frequencies of

250MHz (Table 1). See

Typical Operating Circuit.

Output Mode Control

DIV, MOD, and A=B are input pins that determine the

operating mode of the two output data paths. Six

options are available (Table 1). A typical operating con-

figuration (8:16 demultiplexer mode) is set by 1 on DIV,

0 on MOD, and 0 on A=B. This will give the most

recent sample at AData with the older data on BData.

Both outputs are synchronous and are at half the input

clock rate. To terminate the control inputs, use a resis-

tor to -2V or the equivalent circuit resistor combination

from DGND to -5.2V up to 1k

Ω. When using a diode

pull-up to tie an input high, bias the diode “on” with a

pull-down resistor to avoid input voltage excursions

close to ground. The control inputs are compatible with

standard ECL 10K logic levels over temperature.

Layout, Grounding, and Power Supplies

The MAX100 is designed with separate analog and dig-

ital ground connections to isolate high-current digital

noise spikes. The high-current digital ground, DGND,

is connected to the collectors of the output emitter fol-

lower transistors. The low-current ground connection is

GND, which is a combination of the analog ground and

the ground of the low-current digital decode section.

The DGND and GND connections should be at the

same DC level, and should be connected at only one

location on the board. This will provide better noise

immunity and highest device accuracy. A ground

plane is recommended.

A +5V ±5% supply as well as a -5.2V ±5% supply is

needed for proper operation. Bypass the VEE and

VCC supply pins to GND with high-quality 0.1µF and

0.001µF ceramic capacitors located as close to the

package as possible. An evaluation kit with a suggest-

ed layout is available.