External Clock Operation

To accommodate designs that use an external clock,

the MAX1011’s internal oscillator can be overdriven by

an external clock source (Figure 7). The external clock

source should be a sinusoid to minimize clock phase

noise and jitter, which can degrade the ADC’s ENOB

performance. AC couple the clock source (recom-

mended voltage level is approximately 1Vp-p) to the

oscillator inputs (Figure 7).

Output Data Format

The conversion results are output on a 6-bit-wide data

bus. Data is latched into the ADC output latch following

a pipeline delay of one clock cycle (Figure 8). Output

data is clocked out of the ADC’s data output pins (D0

through D5) on the rising edge of the clock output

3.0ns. The MAX1011 outputs are +3.3V CMOS-logic

compatible.

Transfer Function

Figure 9 shows the MAX1011’s nominal transfer function.

Output coding is offset binary with 1LSB = FSR / 63.

___________Applications Information

The MAX1011 is designed with separate analog and

digital power-supply and ground connections to isolate

high-current digital noise spikes from the more sensi-

tive analog circuitry. The high-current digital output

ground (OGND) and analog ground (GND) should be

at the same DC level, connected at only one location

on the board. This will provide best noise immunity and

improved conversion accuracy. Use of separate

ground planes is strongly recommended.

The entire board needs good DC bypassing for both

analog and digital supplies. Place the power-supply

bypass capacitors close to where the power is routed

onto the board, i.e., close to the connector. 10µF elec-

trolytic capacitors with low-ESR ratings are recom-

mended. For best effective bits performance, minimize

capacitive loading at the digital outputs. Keep the digi-

tal output traces as short as possible.

The MAX1011 requires a +5V ±5% power supply for

GND with high-quality ceramic capacitors located as

close to the package as possible (Table 2). Consult the

evaluation kit manual for a suggested layout and

bypassing scheme.

Low-Power, 90Msps, 6-Bit ADC

8

_______________________________________________________________________________________

Figure 7. External Clock Drive Circuit

MAX1011

CLK

DRIVER

TNK-

TNK+

50

Ω

50

Ω

50

Ω

0.1

µF

0.1

µF

0.01µF

Oscillator/Clock

47pF

Digital Output

9

16

13

BYPASS

TO GND/

OGND

(PIN)

10

6

17

0.01µF

Converter

14

(PIN)

11

SUPPLY

FUNCTION

0.01µF

Analog Inputs

CAPACITOR

VALUE

Table 2. Bypassing Guide

Figure 6. Tank Resonator Oscillator

MAX1011

CLK

DRIVER

VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287

(SOT23 PACKAGE)

INDUCTOR COILCRAFT 1008HS-221.

TNK-

TNK+

220nH

5pF

47pF

47pF

47k

47k

10k