For applications where a DC component of the input

signal is present, Figures 4 and 5 show single-ended

and differential DC-coupled input circuits. The amplifi-

er’s input common-mode voltage range extends from

1.75V to 2.75V. To prevent attenuation of the input

signal’s DC component in this mode, disable the offset-

correction amplifier by grounding the OCC+ and OCC-

pins (Figures 4 and 5).

ADC

The ADC block receives the analog signal from the

input amplifier. The ADC uses flash conversion with 63

fully differential comparators to digitize the analog input

signal into a 6-bit output in offset binary format.

The MAX1011 features a proprietary encoding scheme

that ensures no more than 1LSB dynamic encoding

error. Dynamic encoding errors resulting from meta-

stable states may occur when the analog input voltage,

at the time the sample is taken, falls close to the deci-

sion point for any one of the input comparators. The

resulting output code for typical converters can be

incorrect, including false full- or zero-scale outputs. The

MAX1011’s unique design reduces the magnitude of

this type of error to 1LSB.

Internal Voltage Reference

An internal buffered-bandgap reference is included on

the MAX1011 to drive the ADC’s reference ladder. The

on-chip reference and buffer eliminate any external

(high-impedance) connections to the reference ladder,

minimizing the potential for noise coupling from exter-

nal circuitry while ensuring that the voltage reference,

input amplifier, and reference ladder track well with

variations of temperature and power supplies.

Oscillator Circuit

The MAX1011 includes a differential oscillator, which is

controlled by an external parallel resonant (tank) net-

work as shown in Figure 6. Alternatively, the oscillator

may be overdriven with an external clock source as

shown in Figure 7.

Internal Clock Operation (Tank)

If the tank circuit is used, the resonant inductor should

have a sufficiently high Q and a self-resonant frequen-

cy (SRF) of at least twice the intended oscillator fre-

quency. Coilcraft’s 1008HS-221, with an SRF of

700MHz and a Q of 45, works well for this application.

Generate different clock frequency ranges by adjusting

varactor and tank elements.

An internal clock-driver buffer is included to provide

sharp clock edges to the internal flash comparators.

The buffer ensures that the comparators are simultane-

ously clocked, maximizing the ADC’s effective number

of bits (ENOB) performance.

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________

7

Figure 4. Single-Ended DC-Coupled Input

Figure 5. Differential DC-Coupled Input

MAX1011

INPUT

AMP

20k

2.35V INTERNAL REFERENCE

20k

IN+

OCC+

OCC-

IN-

OFFSET CORRECTION DISABLED

1.75V TO 2.75V

OFFSET

CORREC-

TION

MAX1011

INPUT

AMP

20k

2.35V INTERNAL REFERENCE

20k

IN+

OCC+

OCC-

IN-

OFFSET CORRECTION DISABLED

DIFFERENTIAL SOURCE

WITH COMMON MODE

FROM 1.75V TO 2.75V.

OFFSET

CORREC-

TION