MAX195 datasheet(13/28 Pages) MAXIM

13 / 28 page

16-Bit, 85ksps ADC with 10µA Shutdown

______________________________________________________________________________________

INPUT

SIGNAL

1N914

DIODE

CLAMPS

+5V

AIN

MAX195

-5V

VSSA

VDDA

+15V

-15V

Ω

Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence

REF and AIN Input Protection

The REF and AIN signals should not exceed the

MAX195 supply rails. If this can occur, diode clamp the

signal to the supply rails. Use silicon diodes and a 10

Ω

current-limiting resistor (Figures 10 and 12) or Schottky

diodes without the resistor.

When using the current-limiting resistor, place the resis-

tor between the appropriate input (AIN or REF) and any

bypass capacitor. While this results in AC transients at

the input due to dynamic input currents, the transients

settle quickly and do not affect conversion results.

Improperly placing the bypass capacitor directly at the

input forms an RC lowpass filter with the current-limiting

resistor, which averages the dynamic input current and

causes linearity errors.

Analog Input

The MAX195 uses a capacitive DAC that provides an

inherent track/hold function. The input impedance is

typically 30

Ω in series with 250pF in unipolar mode and

Ω in series with 125pF in bipolar mode.

Input Range

The analog input range can be either unipolar (0V to

VREF) or bipolar (-VREF to VREF), depending on the

state of the BP/UP/SHDN pin (see

Digital Interface sec-

tion). The reference range is 0V to VDDA. When choos-

ing the reference voltage, the equivalent MAX195 input

noise (40µVRMS in unipolar mode, 80µVRMS in bipolar

mode) should be considered.

Input Acquisition and Settling

Four conversion-clock periods are allocated for acquir-

ing the input signal. At the highest conversion rate, four

clock periods is 2.4µs. If more than three clock cycles

have occurred since the end of the previous conver-

sion, conversion begins on the next falling clock edge

after CONV goes low. Otherwise, bringing CONV low

begins a conversion on the fourth falling clock edge

after the previous conversion. This scheme ensures the

minimum input acquisition time is four clock periods.

Most applications require an input buffer amplifier. If

the input signal is multiplexed, the input channel should

be switched near the beginning of a conversion, rather

than near the end of or after a conversion (Figure 13).

This allows time for the input buffer amplifier to respond

to a large step change in input signal. The input amplifi-

er must have a high enough slew rate to complete the

required output voltage change

before the beginning of

the acquisition time.

At the beginning of acquisition, the capacitive DAC is

connected to the amplifier output, causing some output

disturbance. Ensure that the sampled voltage has set-

tled to within the required limits before the end of the

acquisition time. If the frequency of interest is low, AIN

can be bypassed with a large enough capacitor to

charge the capacitive DAC with very little change in

voltage (Figure 14). However, for AC use, AIN must be

driven by a wideband buffer (at least 10MHz), which

must be stable with the DAC’s capacitive load (in paral-

lel with any AIN bypass capacitor used) and also must

settle quickly (Figure 15 or 16).

MAX195 Datasheet(PDF) 13 Page - Maxim Integrated Products

MAX195 Datasheet(HTML) 13 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL