MAX195 datasheet(21/28 Pages) MAXIM

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16-Bit, 85ksps ADC with 10µA Shutdown

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Be sure that digital return currents do not pass through

the analog ground and that return-current paths are low

impedance. A 5mA current flowing through a PC board

ground trace impedance of only 0.05

Ω creates an error

voltage of about 250µV, or about 2LSBs error with a

±4V full-scale system.

The board layout should ensure as much as possible

that digital and analog signal lines are kept separate.

Do not run analog and digital (especially clock) lines

parallel to one another. If you must cross one with the

other, do so at right angles.

The ADC’s high-speed comparator is sensitive to high-

frequency noise on the VDDA and VSSA power sup-

plies. Bypass these supplies to the analog ground

plane with 0.1µF in parallel with 1µF or 10µF low-ESR

capacitors. Keep capacitor leads short for best supply-

noise rejection.

Shutdown

The MAX195 may be shut down by pulling BP/UP/

SHDN low. In addition to lowering power dissipation to

10µW (100µW max) when the device is not in use, you

can save considerable power by shutting the converter

down for short periods between conversions. There is

no need to perform a reset (calibration) after the con-

verter has been shut down unless the time in shutdown

is long enough that the supply voltages or ambient tem-

perature may have changed.

The time required for the converter to “wake up” and

settle depends heavily on the amount of additional error

acceptable. For 0.5LSB additional error, 3.2µs is suffi-

cient settling time and also allows enough time for reac-

quisition of the analog input signal. 50µs settling is

required for less than 0.1LSB error. Figure 23 is a

graph of theoretical power consumption vs. conver-

sions per second for the MAX195 that assumes the

conversion clock is 1.7MHz and the converter is shut

down as much as possible between conversions.

Stop CLK before shutting down the MAX195. CLK must

be stopped without generating short clock pulses. Short

CLK pulses (less than 150ns), or shutting down the

MAX195 without stopping CLK, may adversely affect the

MAX195’s internal calibration data. In applications

where CLK is free-running and asynchronous, use the

circuit of Figure 24 to stop CLK cleanly.

To minimize the time required to settle and perform a

conversion, shut the converter down only after a con-

version is finished and the desired mode (unipolar or

bipolar) has been set. This ensures that the sampling

capacitor array is properly connected to the input sig-

nal. If shut down in mid-conversion, when awakened,

Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)

MAX195 Datasheet(PDF) 21 Page - Maxim Integrated Products

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