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MAX1970EEE Datasheet(PDF) 13 Page - Maxim Integrated Products |
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MAX1970EEE Datasheet(HTML) 13 Page - Maxim Integrated Products |
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13 / 20 page ![]() Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step- Down Regulator with POR and RSI/PFO ______________________________________________________________________________________ 13 the PWM comparator’s inverting input. The PWM com- parator turns off the internal high-side MOSFET when this sum exceeds the integrated feedback voltage. Current Limit The internal MOSFET has a current limit of 1.2A (typ). If the current flowing out of LX_ exceeds this maximum, the high-side MOSFET turns off and the synchronous rectifier MOSFET turns on. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. There is also a synchro- nous rectifier current limit of -0.85A. This is to protect the device from current flowing into LX_. If the negative current limit is exceeded, the synchronous rectifier is turned off, and the inductor current continues to flow through the high-side MOSFET body diode back to the input until the beginning of the next cycle or until the inductor current drops to zero. VCC Decoupling Due to the high-switching frequency and tight output tolerance (±1%), decoupling between IN and VCC is recommended. Connect a 10 Ω resistor between IN and VCC and a 0.1µF ceramic capacitor from VCC to GND. Place the resistor and capacitor as close to VCC as possible. Startup To reduce the supply inrush current, soft-start circuitry ramps up the output voltage during startup. This is done by charging the REF capacitor with a current source of 25µA. Once REF reaches 1.2V, the output is in full regulation. The soft-start time is determined from: Soft-start occurs when power is first applied, and when EN is pulled high with power already present. The part also goes through soft-start when coming out of under- voltage lockout (UVLO) or thermal shutdown. The range of capacitor values for CREF is from 0.01µF to 1.0µF. Undervoltage Lockout If VCC drops below 2.35V, the MAX1970/MAX1971/ MAX1972 assume that the supply voltage is too low to provide a valid output voltage, and the UVLO circuit inhibits switching. Once VCC rises above 2.4V, the UVLO is disabled and the soft-start sequence initiates. Enable A logic-enable input (EN) is provided. For normal oper- ation, drive EN logic high. Driving EN low turns off both outputs, and reduces the input supply current to approximately 1µA. Power-Fail Output The input voltage is sensed for 5V (typical USB applica- tions), and if VCC drops below 3.94V, the power-fail out- put (PFO) goes high. The time from PFO going high to the outputs going out of regulation depends on the oper- ating output voltage and currents, and the upstream 5V bus storage capacitor value, which is 120µF minimum (per USB specification, version 2.0). The lower the oper- ating voltages and currents, and the higher the storage capacitor, the longer the elapsed time. PFO is an open- drain output, and a 10k to 100k pullup resistor to VCC, or either output, is recommended. Power-On Reset Power-on reset (POR) provides a system reset signal. During power-up, POR is held low until both outputs reach 92% of their regulated voltages, POR continues to be held low for a delayed period, and then goes high. This delay time (TD) for MAX1970 is 16.6ms. The MAX1971 and MAX1972 have a delay of 175ms. Figure 2 is an example of a timing diagram. The POR comparator is designed to be relatively immune to short-duration negative-going output glitch- es.The Typical Operating Characteristics gives a plot of maximum transient duration vs. POR comparator over- drive. The graph was generated using a negative-going pulse applied to an output, starting at 100mV above the actual POR threshold, dropping below the POR thresh- old by the percentage indicated as comparator over- drive, and then returning to 100mV above the threshold. The graph indicates the maximum pulse width the output transient can have without causing POR to trip low. Reset Input Reset input (RSI) is an input on the MAX1971 that, when driven high, forces the POR to go low. When RSI goes low, POR goes through a delay time identical to a power-up event. See Figure 2 for timing diagram. RSI allows software to command a system reset. RSI must be high for a minimum period of 1µs in order to initiate the POR. Thermal-Overload Protection Thermal-overload protection limits total power dissipa- tion. When the IC’s junction temperature exceeds TJ = +170°C, a thermal sensor shuts down the device, allowing the IC to cool. The thermal sensor turns the part on again after the junction temperature cools by 20°C. This results in a pulsed output during continuous overload conditions. During a thermal event, POR goes low, PFO goes high, and soft-start is reset. t V I CC SS REF REF REF REF == × × 48 10 4 . |
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