IR3531A_15 datasheet(29/39 Pages) IRF

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4+1 Phase Dual Output Control IC

IR3531A

March 22, 2012 | FINAL | V1.11

OVER-CURRENT CONTROL

Over current protection (OCP) is a latched event that

requires VCC UVLO or ENABLE cycling to clear. OCP is

performed internally by comparing the VDRP pin voltage

against an OC offset voltage that is added to the respective

VDAC pin voltage. This OC offset voltage is adjusted to

match the active number of phases since VDRP represents

average per-phase current. This ensures that the current

limit is correctly adjusted during phase shedding operation.

An over current condition is registered if the VDRP pin

voltage, which is proportional to the average current plus

VDAC voltage, exceeds the VDAC+ OC offset voltage.

Figure 14 shows the over-current control with delay during

various soft start events. A fixed 256μs OC delay is needed

to protect against nuisance over-current conditions which

can occur as part of normal operation or due to inrush

currents.

ENABLE or VCC UVLO cycling clears the OCP fault latch.

It is recommended to allow sufficient thermal relaxation

time prior to repeat re-enabling to ensure the converter

does not thermally run away. Approximately 4ms thermal

relaxation is recommended for most designs. If ENABLE

is cycled during this relaxation period, the converter will

wait until the internal VDAC has returned to 0V prior to

attempting another power up. The internal VDAC slews at

5mV/µsec and therefore the rise and fall slew durations

are 300µsec for a BOOT of 1.5V. The VDAC pin slews down

to 250mV and does not slew to 0V. This is done to ensure

the current reporting system has enough headroom to

properly operate.

If an over-current occurs during soft start, the control IC

will not disable the voltage regulator until the over current

delay time has elapsed. If the over-current condition

persists after delay time is reached, the fault latch will be

set pulling the error amplifier’s output low and inhibiting

switching in the driver ICs.

IOUT

OCP Threshold

VOUT

Internal VDAC

TRACK

256us OC Delay

ENABLE Cycle does not have an effect on VOUT until

VDAC has reset to 0V. User must ensure proper

thermal relaxation has occurred prior to re-enabling.

ENABLE

ENABLE Cycle after a

recommended 4ms

relaxation timeout

VRRDY momentarily goes high once

VDAC reaches BOOT and then faults

once TRACK-VOUT exceeds 200mV.

VRRDY

VRRDY remains low because TRACK-

VOUT exceeds 200mV prior to VDAC

reaching BOOT.

VRRDY momentarily goes high once

VDAC reaches BOOT and then faults

once TRACK-VOUT exceeds 200mV.

VDAC controls VOUT power up

when TRACK remains high

Recommend ~4ms

Relaxation Delay

VDAC Pin

Figure 14: Over Current Waveforms

IR3531A Datasheet(PDF) 29 Page - International Rectifier

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