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9DB433 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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9DB433 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
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6 / 17 page  9DB433 FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 6 9DB433 REV G 08/25/15 Electrical Characteristics–Clock Input Parameters Electrical Characteristics–Current Consumption Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage - DIF_IN VIHDIF Differential inputs (single-ended measurement) 600 800 1150 mV 1 Input Low Voltage - DIF_IN VILDIF Differential inputs (single-ended measurement) VSS - 300 0 300 mV 1 Input Common Mode Voltage - DIF_IN VCOM Common Mode Input Voltage 300 1000 mV 1 Input Amplitude - DIF_IN VSWING Peak to Peak value (single-ended) 300 1450 mV 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 1 8 V/ns 1,2 Input Leakage Current IIN VIN = VDD , VIN = GND -5 -0.02 5 uA 1 Input Duty Cycle dtin Measurement from differential waveform 45 50 55 % 1 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 125 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2Slew rate measured through +/-75mV window centered around differential zero TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Supply Current IDD3.3OP All outputs active @100MHz, CL = Full load; 170 200 mA 1 IDD3.3PD All diff pairs driven 53 60 mA 1 IDD3.3PDZ All differential pairs tri-stated 3 6 mA 1 1Guaranteed by design and characterization, not 100% tested in production. Powerdown Current TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES -3dB point in High BW Mode (TIND)1.5 2.7 4.1 MHz 1 -3dB point in High BW Mode (TCOM)2 2.7 4 MHz 1 -3dB point in Low BW Mode 0.7 1.1 1.4 MHz 1 PLL Jitter Peaking tJPEAK Peak Pass band Gain 1.5 2 dB 1 Duty Cycle tDC Measured differentially, PLL Mode 45 49 55 % 1 Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz -2 2 % 1,4 Bypass Mode, VT = 50% (TIND) 2500 4900 ps 1 Bypass Mode, VT = 50% (TCOM) 2500 4500 ps 1,5 tpdPLL PLL Mode VT = 50% -250 -50 250 ps 1 Skew, Output to Output tsk3 VT = 50% 50/60 ps 1,5 PLL mode 50 ps 1,3 Additive Jitter in Bypass Mode 50 ps 1,3 1Guaranteed by design and characterization, not 100% tested in production. 2 I REF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 3 Measured from differential waveform 4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 5 First number is commercial temp, second number is industrial temp. tpdBYP Jitter, Cycle to cycle tjcyc-cyc PLL Bandwidth BW Skew, Input to Output |
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