ICS87004AGI REVISION D JANUARY 4, 2010

11

©2009 Integrated Device Technology, Inc.

ICS87004I Data Sheet

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 3A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

Figure 3A. CLK/nCLK Input Driven by an IDT Open

Emitter LVHSTL Driver

Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL

Driver

Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL

Driver

Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL

Driver

Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver

R1

50

R2

50

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

HiPerClockS

LVHSTL Driver

Differential

Input

R3

125

R4

125

R1

84

R2

84

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

3.3V

LVPECL

Differential

Input

HCSL

*R3

33

*R4

33

CLK

nCLK

2.5V

3.3V

Zo = 50

Ω

Zo = 50

Ω

Differential

Input

R1

50

R2

50

*Optional – R3 and R4 can be 0

Ω

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

R1

50

R2

50

R2

50

3.3V

R1

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

R2

120

R3

120

R4

120