MAX5152BEEE datasheet(5/20 Pages) MAXIM

5 / 20 page

Low-Power, Dual, 13-Bit Voltage-Output DACs

with Configurable Outputs

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ELECTRICAL CHARACTERISTICS—MAX5153 (continued)

(VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values

are at TA = +25°C, output buffer connected in unity-gain configuration (Figure 9).)

CS = VDD, fDIN = 100kHz, VSCLK = 3Vp-p

(Note 4)

(Note 7)

Rail-to-rail (Note 6)

To 1/2LSB of full-scale, VSTEP = 1.25V

tCL

SCLK Pulse Width Low

CONDITIONS

tCH

SCLK Pulse Width High

nV-s

Digital Crosstalk

nV-s

Digital Feedthrough

µs

Time Required to Exit

Shutdown

µA

±0.1

IFB_

Current into FBA or FBB

100

tCP

SCLK Clock Period

µA

±1

Reference Current in

Shutdown

µA

IDD(SHDN)

Power-Supply Current in

Shutdown

0.5

0.6

IDD

Power-Supply Current

2.7

3.6

VDD

Positive Supply Voltage

tDS

DIN Setup Time

tCHS

SCLK Rise to CS Rise Hold

Time

tCSS

CS Fall to SCLK Rise Setup

Time

CLOAD = 200pF

0 to VDD

Output Voltage Swing

µs

Output Settling Time

CLOAD = 200pF

120

V/µs

0.75

Voltage Output Slew Rate

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

tDO2

SCLK Fall to DOUT Valid

Propagation Delay

120

tDO1

SCLK Rise to DOUT Valid

Propagation Delay

tDH

DIN Hold Time

100

tCSW

CS Pulse Width High

tCS1

CS Rise to SCLK Rise Hold

tCS0

SCLK Rise to CS Fall Delay

Note 4: SCLK minimum clock period includes rise and fall times.

Note 5: Accuracy is specified from code 40 to code 8191.

Note 6: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 100mV. Guaranteed by PSRR test at the end

points.

Note 7: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞.

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

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