MAX533BEEE datasheet(14/16 Pages) MAXIM

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Power Sequencing

The voltage applied to REF should not exceed VDD at

any time. If proper power sequencing is not possible,

connect an external Schottky diode between REF and

VDD to ensure compliance with the absolute maximum

ratings. Do not apply signals to the digital inputs before

the device is fully powered up.

Power-Supply Bypassing

and Ground Management

Connect AGND and DGND together at the IC. This

ground should then return to the highest-quality ground

available. Bypass VDD with a 0.1µF capacitor, located

as close to VDD and DGND as possible.

Careful PC board layout minimizes crosstalk among

DAC outputs and digital inputs. Figure 10 shows sug-

gested circuit board layout to minimize crosstalk.

Unipolar-Output,

Two-Quadrant Multiplication

In unipolar operation, the output voltages and the refer-

ence input are the same polarity. Figure 11 shows the

MAX533 unipolar configuration, and Table 2 shows the

unipolar code.

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

______________________________________________________________________________________

Table 2. Unipolar Code Table

Note: 1LSB = (VREF) (2-8) = +VREF (––––)

256

+VREF (––––)

256

0 0 0 1

0 0 0 0

127

+VREF (––––)

256

1 1 1 1

0 1 1 1

128

VREF

+VREF (––––) = + ––––

256

0 0 0 0

1 0 0 0

129

+VREF (––––)

256

0 0 0 1

1 0 0 0

255

+VREF (––––)

256

1 1 1 1

ANALOG

OUTPUT

LSB

MSB

DAC CONTENTS

DAC CODE

NEGATIVE

OFFSET

OUTPUT

VOLTAGE

Figure 9. Effect of Negative Offset (Single Supply)

REF

R15

R16

R255

LSB DECODER

DAC A

Figure 8. DAC Simplified Circuit Diagram

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