HIGH-WITHSTAND VOLTAGE LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

S-1142C/D Series

Seiko Instruments Inc.

11



Standard Circuit

*1

*2

Input

Output

GND

Single GND

VOUT

VIN

VSS

ON / OFF

*2. A ceramic capacitor of 0.1

Figure 10

Caution The above connection diagram and constants will not guarantee successful operation. Perform

thorough evaluation using an actual application to set the constants.



Condition of Application

0.1

μF or more

0.1

μF or more

Caution Generally a series regulator may cause oscillation, depending on the selection of external parts.

Confirm that no oscillation occurs in the application for which the above capacitors are used.



The S-1142C/D Series requires an output capacitor between the VOUT pin and the VSS pin for phase compensation.

Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1

μF or more over the entire

temperature range. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the

capacitance must be 0.1

μF or more.

The values of output overshoot and undershoot, which are transient response characteristics, vary depending on the

value of the output capacitor.

The required value of capacitance for the input capacitor differs depending on the application.

≥ 0.1 μF

≥ 0.1 μF

characteristics under the actual usage conditions.