S1142C datasheet(13/32 Pages) SII

13 / 32 page

HIGH-WITHSTAND VOLTAGE LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

Rev.1.2_00

S-1142C/D Series

Seiko Instruments Inc.



Operation

1. Basic operation

Figure 11 shows the block diagram of the S-1142C/D Series.

The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage

resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the

constant output voltage which is not influenced by the input voltage and temperature change, to the output

transistor.

VOUT

VSS

VIN

Error amplifier

Current

supply

Vref

Vfb

−

Reference voltage

circuit

*1. Parasitic diode

Figure 11

2. Output transistor

In the S-1142C/D Series, a low on-resistance P-channel MOS FET is used as the output transistor.

Be sure that VOUT does not exceed VIN

+ 0.3 V to prevent the voltage regulator from being damaged due to

reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of VOUT

became higher than VIN.

S1142C Datasheet(PDF) 13 Page - Seiko Instruments Inc