+2.5V to +5.5V, Low-Power, Single/Dual,

8-Bit Voltage-Output DACs in µMAX Package

6

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_______________Detailed Description

Analog Section

The MAX548A/MAX549A/MAX550A are 8-bit, voltage-

output digital-to-analog converters (DACs). The

MAX548A/MAX549A are dual DACs, and the MAX550A

is a single DAC. Each DAC consists of an R-2R ladder

network that converts 8-bit digital inputs into equivalent

analog output voltages in proportion to the applied ref-

erence voltage (Figure 1).

The DACs feature double-buffered inputs and

unbuffered outputs. The MAX549A/MAX550A require

an external reference. The MAX548A’s reference inputs

range is from +2.5V to +5.5V.

Reference Input

the full-scale output for all the DACs and may range

dependent, with the lowest value occurring with code

01010101 (55 hex). To minimize INL errors, the refer-

ence voltage source should have less than 3

Ω output

impedance.

DAC Output

The MAX548A/MAX549A/MAX550A contain DACs with

unbuffered outputs; each output connects directly to an

R-2R ladder. Typical output impedance is 33.3k

Ω. This

configuration minimizes power consumption and

reduces offset errors. For highest accuracy, apply high

resistive loads (1M

Ω and up). Lower resistive loads can

be driven, but output loading increases full-scale error.

The magnitude of the expected error is the ratio of the

DAC output resistance to the DC load resistance at the

output.

Typically, an energy pulse is coupled into the DAC out-

put on CS’s rising edge. Since each DAC output is

unbuffered, connecting a small capacitor (200pF to

1000pF) from the output to ground creates a lowpass

filter that effectively suppresses the pulse for sensitive

applications (see

Typical Operating Characteristics).

Shutdown Mode

When the MAX548A/MAX549A/MAX550A are in shut-

down mode, the R-2R ladder disconnects from the refer-

ence source. The MAX549A/MAX550A supply current

does not change, but the REF input current decreases to

less than 1µA. This allows the externally applied system

reference to remain active with minimal power

consumption. The MAX548A supply current also

decreases to less than 1µA in shutdown mode. When the

MAX548A/MAX549A/MAX550A exit shutdown mode,

recovery time is equivalent to the DAC’s settling time.

Serial Interface

The serial interface is SPI/QSPI and Microwire compati-

ble. An active-low chip select (CS) enables the input

shift register to receive data from the serial input (DIN).

Data is clocked into the shift register on the rising edge

of the serial-clock signal (SCLK). The clock frequency

can be as high as 10MHz.

Transmit data MSB first in one 16-bit word or two 8-bit

bytes. The write cycle can be segmented to allow two

8-bit-wide transfers when CS remains low. After all 16

bits are clocked into the input shift register, a rising

2R

R

R

R

R

2R

2R

2R

2R

2R

REF

GND

NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FF HEX.

DAC_ REGISTER

OUT_

MSB

LSB

GND

2R

R

R

R

2R

2R

2R

2R

Figure 1. DAC Simplified Circuit Diagram