S1002 datasheet(17/39 Pages) SII

17 / 39 page

VOLTAGE DETECTOR WITH SENSE PIN

Rev.1.1_00

S-1002 Series

Seiko Instruments Inc.

1. 2 S-1002 Series CA / CB type

(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage

(VSENSE) is the release voltage (

+VDET) or higher, the Nch transistor is turned off and the Pch transistor is turned

on to output VDD ("H"). Since the Nch transistor (N1) is turned off, the input voltage to the comparator is

(RB

+ RC ) • VSENSE

+ RB + RC

(2) Even if VSENSE decreases to

+VDET or lower, VDD is output when VSENSE is higher than the detection voltage

(

−VDET).

When VSENSE decreases to

−VDET or lower (point A in Figure 24), the Nch transistor is turned on and the Pch

transistor is turned off. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time

(tDET).

At this time, N1 is turned on, and the input voltage to the comparator is

• VSENSE

+ RB

(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is

stable when VDD is minimum operation voltage or higher.

(4) Even if VSENSE exceeds

−VDET, VSS is output when VSENSE is lower than +VDET.

(5) When VSENSE increases to

+VDET or higher (point B in Figure 24), the Nch transistor is turned off and the Pch

transistor is turned on. And then VDD is output from the OUT pin after the elapse of the release delay time

(tRESET).

VSS

VREF

−

OUT

VDD

SENSE

VDD

VSENSE

Nch

Pch

*1.

Parasitic diode

Figure 23 Operation of S-1002 Series CA / CB Type

VSENSE

VSS

VDD

VSS

(1)

(2) (3)

(5)

(4)

tDET

tRESET

Hysteresis width

(VHYS)

Minimum operation voltage

Output from OUT pin

Release voltage (

+VDET)

Detection voltage (

−VDET)

Figure 24 Timing Chart of S-1002 Series CA / CB Type

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