UCD3138128 datasheet(12/80 Pages) TI

12 / 80 page

UCD3138128, UCD3138A64

SLUSBZ8A – JUNE 2014 – REVISED SEPTEMBER 2014

www.ti.com

Timing Characteristics (continued)

V33A = V33D = V33DIO = 3.3V; 1

μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Program time to write one word in data

µs

flash

Sync-in/sync-out pulse width

Sync pin

256

POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)

Time delay after Power is good or

tPOR

RESET* relinquished

IRESET goes from a low state to a high

The time it takes from the device to exit a

state. This is approximately equivalent

tEXC1

reset state and begin executing the boot

0.5

to toggling the external reset pin from

flash.(1)

low to high state.

IRESET goes from a low state to a high

The time it takes from the device to exit a

state. This is approximately equivalent

tEXC2

reset state and begin executing program

to toggling the external reset pin from

flash bank 0 (32 kB).(1)

low to high state.

IRESET goes from a low state to a high

The time it takes from the device to exit a

state. This is approximately equivalent

tEXCT

reset state and begin executing the total

to toggling the external reset pin from

program flash (64 kB).(1)

low to high state.

TEMPERATURE SENSOR(1)

tON

Turn on time / settling time of sensor

100

μs

ANALOG COMPARATOR

Bits

bits

INL(3)

–0.42

0.21

LSB

DNL(3)

0.06

0.12

LSB

Time to disable DPWM output based on 0

V to 2.5 V step input on the analog

150

comparator.(3)

(3)

Characterized by design and not production tested.

8.7 PMBUS/SMBUS/IC Timing

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and

PMBus in Slave or Master mode are shown in the Timing Requirements, Figure 1, and Figure 2. The numbers in

the Timing Requirements are for 400 kHz operating frequency. However, the device supports two speeds,

standard (100 kHz) and fast (400 kHz).

8.8 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)

fSMB

SMBus/PMBus operating frequency

Slave mode, SMBC 50% duty cycle

100

400

kHz

fI2C

I2C operating frequency

Slave mode, SCL 50% duty cycle

100

400

kHz

Bus free time between start and

t(BUF)

1.3

µs

stop(1)

t(HD:STA)

Hold time after (repeated) start(1)

0.6

µs

t(SU:STA)

Repeated start setup time(1)

0.6

µs

t(SU:STO)

Stop setup time(1)

0.6

µs

t(HD:DAT)

Data hold time

Receive mode

t(SU:DAT)

Data setup time

100

t(TIMEOUT)

Error signal/detect(2)

t(LOW)

Clock low period

1.3

µs

(1)

Fast mode, 400 kHz

(2)

The device times out when any clock low exceeds t(TIMEOUT).

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