1-Cell to 3-Cell, High-Power,

Low-Noise, Step-Up DC-DC Converters

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3

ELECTRICAL CHARACTERISTICS (continued)

unless otherwise noted.)

Input Low Voltage

Accuracy

V

Current into OUT pin, CLK/SEL = GND

monotonic to 8 bits

±4

% FSR

Internal Trip Level

µA

2.95

3.10

V

External Trip Level

Input High Voltage

1.225

1.275

µA

1

2

AIN1, AIN2 Input Current

V

0

2.5

AINSEL = OUT

AIN2 Input Voltage Range

V

0.625

1.875

AINSEL = GND

AIN1 Input Voltage Range

V

V

Data Output Voltage High

V

0.4

Data Output Voltage Low

POK Low Voltage

0.4

V

POK High Leakage Current

0.01

1

µA

POKIN Leakage Current

V

50

nA

35

90

Operating Current in Low-Power

Mode (Note 6)

Logic Input Current

ON1, ON2, AINSEL and CLK/SEL

1

µA

Internal Oscillator Frequency

CLK/SEL = OUT

260

300

340

kHz

Oscillator Maximum Duty Cycle

80

85

90

%

External Clock Frequency Range

200

400

kHz

CLK/SEL Pulse Width

Not tested

200

ns

CLK/SEL Rise/Fall Time

Not tested

100

ns

Current into OUT pin, CLK/SEL = OUT,

does not include switching losses

µA

150

300

UNITS

MIN

TYP

MAX

CONDITIONS

PARAMETER

Operating Current in Low-Noise

Mode (Note 6)

µA

0.1

20

POUT Leakage Current

µA

0.1

20

LX Leakage Current

N-channel

0.3

0.6

CLK/SEL = GND

0.13

0.25

CLK/SEL = OUT

P-channel

Ω

0.25

0.5

Switch On-Resistance

CLK/SEL = OUT

600

800

1000

MAX848

CLK/SEL = OUT

1100

1350

1600

MAX849

120

200

300

MAX848

mA

250

400

550

N-Channel Current Limit

MAX849

DC-DC SWITCHES

ADC

POWER-GOOD

LOGIC AND CONTROL INPUTS