Micropower, Ultra-Small, Single/Dual/Quad,

Single-Supply Comparators

6

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2) The hysteresis band will be:

and

4) Select R2. In this example, we will choose 1k

Ω.

6) Solve for R1.

0.050V = 5(1000

Ω/(R1 + 1000Ω)) V

where R1

The above-described design procedure assumes rail-

to-rail output swing. If the output is significantly loaded,

the results should be corrected.

Board Layout and Bypassing

Use 100nF bypass as a starting point. Minimize signal

trace lengths to reduce stray capacitance. Minimize the

capacitive coupling between IN- and OUT. For slow-

moving input signals (rise time > 1ms), use a 1nF

capacitor between IN+ and IN-.

Biasing for Data Recovery

Digital data is often embedded into a bandwidth and

amplitude-limited analog path. Recovering the data can

be difficult. Figure 2 compares the input signal to a

time-averaged version of itself. This self-biases the

threshold to the average input voltage for optimal noise

margin. Even severe phase distortion is eliminated from

the digital output signal. Be sure to choose R1 and C1

so that:

digital data stream.

MAX9021

OUT

IN+

IN-

R2

R1

Figure 1. Additional Hysteresis

MAX9021

OUT

IN+

IN-

10k

Ω

0.1

µF

Figure 2. Time Averaging of the Input Signal for Data Recovery