Dual LVDS Line Receiver

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5

0.6

0.5

0.4

0.3

0.2

-40

10

-15

35

60

85

TRANSITION TIME vs. TEMPERATURE

TEMPERATURE (

°C)

2.0

2.4

2.2

2.8

2.6

3.0

3.2

3.4

3.6

10

20

25

15

30

35

40

45

50

PROPAGATION DELAY

vs. LOAD CAPACITANCE

LOAD CAPACITANCE (pF)

0

0.4

0.6

0.2

1.0

0.8

1.4

1.2

1.6

2.0

1.8

2.2

10

20

25

15

30

35

40

45

50

TRANSITION TIME

vs. LOAD CAPACITANCE

LOAD CAPACITANCE (pF)

Typical Operating Characteristics (continued)

Detailed Description

LVDS is intended for point-to-point communication over

a controlled-impedance medium as defined by the

ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS

uses a lower voltage swing than other common commu-

nication standards, achieving higher data rates with

reduced power consumption, while reducing EMI

emissions and system susceptibility to noise.

The MAX9159 is a dual LVDS line receiver ideal for

applications requiring high data rates, low power, and

low noise. The device accepts an LVDS input and

translates it to an LVTTL output. The receiver detects

differential signals as low as 100mV and as high as

0.6V within an input voltage range of 0 to 2.4V.

The 250mV to 450mV differential output of an LVDS dri-

ver is nominally centered around a 1.25V offset. This

offset, coupled with the receiver’s 0 to 2.4V input volt-

age range, allows an approximate ±1V shift in the sig-

nal (as seen by the receiver). This allows for a

difference in ground references of the driver and the

receiver, the common-mode effects of coupled noise,

or both. The LVDS standards specify an input voltage

range of 0 to 2.4V referenced to receiver ground.

Fail-Safe

The fail-safe feature of the MAX9159 sets the output

high and reduces supply current when:

• Inputs are open.

• Inputs are undriven and shorted.

• Inputs are undriven and terminated.

A fail-safe circuit is important because under these

conditions, noise at the input may switch the receiver

and it may appear to the system that data is being

received. Open or undriven terminated input conditions

can occur when a cable is disconnected or cut, or

when an LVDS driver output is in high impedance. A

short condition can occur because of a cable failure.

The fail-safe input network (Figure 1) samples the input

(nominal). When the input is driven to levels specified in

the LVDS standards, the input common-mode voltage is

PIN

NAME

FUNCTION

Power Supply

2

1Y

Channel 1 Output

3

2Y

Channel 2 Output

4

GND

Ground

5

2B

Channel 2 Inverting Differential Input

6

2A

Channel 2 Noninverting Differential Input

7

1B

Channel 1 Inverting Differential Input

8

1A

Channel 1 Noninverting Differential Input

Pin Description