Dual LVDS Line Receiver

6

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vated. If the inputs are open or if the inputs are undriven

and shorted or undriven and parallel terminated, there is

no input current. In this case, a pullup resistor in the fail-

the fail-safe circuit and forcing the output high.

Applications Information

Power-Supply Bypassing

ic 0.1µF and 0.001µF capacitors in parallel as close to

the device as possible, with the smaller value capacitor

closest to the device.

Differential Traces

Input trace characteristics affect the performance of the

MAX9159. Use controlled-impedance PC board traces,

typically 100

Ω. Match the termination resistor to this

characteristic impedance. Eliminate reflections and

ensure that noise couples as common mode by running

the differential traces close together. Reduce skew by

matching the electrical length of the traces. Excessive

skew can result in a degradation of magnetic field can-

cellation. Input differential signals should be routed

close to each other to cancel their external magnetic

field. Maintain a constant distance between the differ-

ential traces to avoid discontinuities in differential

impedance. Minimize the number of vias to further pre-

vent impedance discontinuities.

Cables and Connectors

Transmission media should typically have a controlled

differential impedance of 100

Ω. Use cables and con-

nectors that have matched differential impedance to

minimize impedance discontinuities. Avoid the use of

unbalanced cables such as ribbon or simple coaxial

cable. Balanced cables such as twisted pair offer

superior signal quality and tend to generate less EMI

due to canceling effects. Balanced cables tend to pick

up noise as common mode, which is rejected by the

LVDS receiver.

Termination

In point-to-point connections, the MAX9159 requires an

external termination resistor. The termination resistor

should match the differential impedance of the transmis-

sion line. Termination resistance is typically 100

Ω, but

may range between 90

Ω to 132Ω, depending on the

characteristic impedance of the transmission medium.

When using the MAX9159, minimize the distance

between the input termination resistor and the

MAX9159 inputs. Use 1% surface-mount resistors.

Board Layout

For LVDS applications, use a four-layer PC board with

separate layers for power, ground, and input/output. To

minimize crosstalk, do not run the output in parallel with

the inputs.

Chip Information

TRANSISTOR COUNT: 461

PROCESS: CMOS

_A

_B

GND

_Y

MAX9159

Figure 1. Input Fail-Safe Network

MAX9159

PULSE

GENERATOR

_Y

*50

Ω REQUIRED FOR PULSE GENERATOR.

_A

_B

*50

Ω

*50

Ω

Figure 2. Propagation Delay and Transition-Time Test Circuit

20%

20%

1.4V

1.4V

80%

80%

1.4V

1V

Figure 3. Propagation Delay and Transition-Time Waveforms