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OMAP4470 Datasheet(PDF) 18 Page - Texas Instruments |
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OMAP4470 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 450 page  Public Version OMAP4470 SWPS048A – AUGUST 2012 – REVISED JANUARY 2013 www.ti.com 5-159 Low- / Full-Speed USBB2 Timing Conditions—Bidirectional Standard 3-pin Mode—1.8 V .......................... 346 5-160 Low- / Full-Speed USBB2 Timing Requirements—Bidirectional Standard 3-pin Mode—1.8 V ...................... 346 5-161 Low- / Full-Speed USBB2 Switching Characteristics—Bidirectional Standard 3-pin Mode—1.8 V .................. 347 5-162 Low- / Full-Speed USBB2 Timing Conditions—Bidirectional TLL 3-pin Mode—1.8 V ................................. 347 5-163 Low- / Full-Speed USBB2 Timing Requirements—Bidirectional TLL 3-pin Mode—1.8 V ............................. 348 5-164 Low- / Full-Speed USBB2 Switching Characteristics—Bidirectional TLL 3-pin Mode—1.8 V ........................ 348 5-165 Low- / Full-Speed USBB2 Timing Conditions—Bidirectional 2-pin Mode—1.8 V ...................................... 349 5-166 Low- / Full-Speed USBB2 Timing Requirements—Bidirectional 2-pin Mode—1.8 V .................................. 349 5-167 High-Speed USBB2 Timing Conditions—ULPI SDR Mode ............................................................... 350 5-168 High-Speed USBB2 Timing Requirements—ULPI SDR Mode—Slave Mode .......................................... 350 5-169 High-Speed USBB2 Switching Characteristics—ULPI SDR Mode—Slave Mode ...................................... 350 5-170 High-Speed USBB2 Timing Conditions—ULPI TLL Mode—Master Mode .............................................. 351 5-171 High-Speed USBB2 Timing Requirements—ULPI TLL Mode—Master Mode .......................................... 352 5-172 High-Speed USBB2 Switching Characteristics—ULPI TLL Mode—Master Mode ..................................... 352 5-173 High-Speed USBB2—HSIC DDR Timing Conditions—1.2 V ............................................................. 353 5-174 High-Speed USBB2 Timing Requirements—HSIC DDR Receive Mode—1.2 V ....................................... 354 5-175 High-Speed USBB2 Switching Characteristics—HSIC DDR Transmit Mode—1.2 V .................................. 354 5-176 I 2C and SmartReflex—Standard and Fast Modes .......................................................................... 355 5-177 I 2C and SmartReflex—High-Speed Mode ................................................................................... 356 5-178 I 2C and SmartReflex Correspondence Standard vs Data Manual Timing References ................................ 357 5-179 HDQ/1-Wire Timing Requirements—HDQ Mode ........................................................................... 358 5-180 HDQ Sampling Cases .......................................................................................................... 358 5-181 HDQ/1-Wire Switching Characteristics—HDQ Mode ...................................................................... 358 5-182 HDQ/1-Wire Timing Requirements—1-Wire Mode ......................................................................... 359 5-183 HDQ/1-Wire Switching Characteristics—1-Wire Mode .................................................................... 359 5-184 UART IO Settings References ................................................................................................ 361 5-185 UART Switching Characteristics .............................................................................................. 364 5-186 UART3 IrDA Signaling Rate and Pulse Duration with 3/16 th Encoding—Receive Mode .............................. 368 5-187 UART3 IrDA Rise and Fall Times—Receive Mode ........................................................................ 368 5-188 UART3 IrDA Signaling Rate and Pulse Duration with 3/16 th Encoding—Transmit Mode ............................. 369 5-189 MMC/SD/SDIO 1 Interface Timing Conditions—SD Identification and Standard SD Mode .......................... 370 5-190 MMC/SD/SDIO 1 Interface Timing Requirements—SD Identification and Standard SD Mode ...................... 371 5-191 MMC/SD/SDIO 1 Interface Switching Characteristics—SD Identification and Standard SD Mode .................. 371 5-192 MMC/SD/SDIO 1 Interface Timing Conditions—High-Speed SD Mode ................................................. 372 5-193 MMC/SD/SDIO 1 Interface Timing Requirements—High-Speed SD Mode ............................................. 373 5-194 MMC/SD/SDIO 1 Interface Switching Characteristics—High-Speed SD Mode ........................................ 373 5-195 MMC/SD/SDIO 1 Interface Timing Conditions—High-Speed SDR50 Mode ............................................ 375 5-196 MMC/SD/SDIO 1 Interface Timing Requirements—High-Speed SDR50 Mode ........................................ 375 5-197 MMC/SD/SDIO 1 Interface Switching Characteristics—High-Speed SDR50 Mode ................................... 376 5-198 MMC/SD/SDIO 1 Interface Timing Conditions—High-Speed SD Mode—DDR50 ..................................... 377 5-199 MMC/SD/SDIO 1 Interface Timing Requirements—High-Speed SD Mode—DDR50 ................................. 377 5-200 MMC/SD/SDIO 1 Interface Switching Characteristics—High-Speed SD Mode—DDR50 ............................. 378 5-201 MMC/SD/SDIO 2 Interface Timing Conditions—High-Speed SDR JC64 Mode ........................................ 379 5-202 MMC/SD/SDIO 2 Interface Timing Requirements—High-Speed SDR JC64 Mode .................................... 380 5-203 MMC/SD/SDIO Interface 2 Switching Characteristics—High-Speed SDR JC64 Mode ............................... 380 5-204 MMC/SD/SDIO 2 Interface Timing Conditions—High-Speed DDR JC64 Mode ........................................ 382 5-205 MMC/SD/SDIO 2 Interface Timing Requirements—High-Speed DDR JC64 Mode .................................... 382 5-206 MMC/SD/SDIO 2 Interface Switching Characteristics—High-Speed DDR JC64 Mode ............................... 383 18 List of Tables Copyright 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