MIC2183

Micrel

MIC2183

10

December 10, 2001

1.5V

Typical

140mV

Hysteresis

(typical)

EN/UVLO

(7)

MIC2183

R1

R2

Bias

Circuitry

Figure 3. UVLO Circuitry

The line voltage turn on trip point is:

VV

R

RR

INPUT ENABLE

THRESHOLD

_

=×

+

2

12

where:

V

comparator reference, typically 1.5V

The input voltage hysteresis is equal to:

VV

RR

R

INPUT HYST

HYST

_

=×

+

12

2

where:

V

typically 140mV.

V

The MIC2183 will be disabled when the input voltage drops

back down to:

V

V

(V

+

R

RR

2

12

Either of 2 UVLO conditions will pull the soft start capacitor

low.

• When the V

undervoltage lockout level.

• When the enable pin drops below the its enable

threshold

The internal bias circuit generates an internal 1.245V band-

gap reference voltage for the voltage error amplifier and a 3V

V

be decoupled with a 1

µF ceramic capacitor. The capacitor

must be placed close to the V

capacitor must be connected directly to the ground plane.

MOSFET Gate Drive

The MIC2183 is designed to drive a high side P-channel

MOSFET and a low side N-channel MOSFET. The source pin

of the P-channel MOSFET is connected to the input of the

power supply. It is turned on when OUTP pulls the gate of the

MOSFET low. The advantage of using a P-channel MOSFET

is that it does not required a bootstrap circuit to boost the gate

voltage higher than the input, as would be required for an N-

channel MOSFET.

The V

drive pins, OUTN and OUTP. V

to the input supply. The V

connected to the same potential.

A non-overlap time is built into the MOSFET driver circuitry.

This dead-time prevents the high-side and low-side MOSFET

drivers from being on at the same time. Either an external

diode or the low-side MOSFET internal parasitic diode con-

ducts the inductor current during the dead-time.

MOSFET Selection

The P-channel MOSFET must have a V

equal to or lower than the input voltage when used in a buck

converter topology. There is a limit to the maximum gate

charge the MIC2183 will drive. Higher gate charge MOSFETs

will slow down the turn-on and turn-off times of the MOSFETs.

Slower transition times will cause higher power dissipation in

the MOSFETs due to higher switching transition losses. The

MOSFETs must be able to completely turn on and off within

the driver non-overlap time If both MOSFETs are conducting

at the same time, shoot-through will occur, which greatly

increases power dissipation in the MOSFETs and reduces

converter efficiency.

The MOSFET gate charge is also limited by power dissipation

in the MIC2183. The power dissipated by the gate drive

circuitry is calculated below:

P

f

GATE

IN

S

××

where: Qgate is the total gate charge of both the N and P-

channel MOSFETs.

f

V

The graph in Figure 4 shows the total gate charge that can be

driven by the MIC2183 over the input voltage range, for

different values of switching frequency.

40

50

60

70

80

90

100

110

120

130

140

3

5

7

9

11

13

15

INPUT VOLTAGE (V)

Frequency vs.

Max. Gate Charge

200kH

600kHz

500kHz

400kHz

300kHz

Figure 4. MIC2183 Frequency vs Max. Gate Charge

Oscillator & Sync

The internal oscillator is free running and requires no external

components. The f/2 pin allows the user to select from two

switching frequencies. A low level set the oscillator frequency

to 400kHz and a high level set the oscillator frequency to

200kHz. The maximum duty cycle for both frequencies is

100%. This is another advantage of using a P-channel

MOSFET for the high-side drive; it can continuously turned

on.

A frequency foldback mode is enabled if the voltage on the

feedback pin (pin 6) is less than 0.3V. In frequency foldback,