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MIC2183 Datasheet(PDF) 11 Page - Micrel Semiconductor |
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MIC2183 Datasheet(HTML) 11 Page - Micrel Semiconductor |
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11 / 12 page ![]() December 10, 2001 11 MIC2183 MIC2183 Micrel the oscillator frequency is reduced by approximately a factor of 4. Frequency foldback is used to limit the energy delivered to the output during a short circuit fault condition. The SYNC input (pin 11) lets the MIC2183 synchronize with an external clock signal. The rising edge of the sync signal generates a reset signal in the oscillator, which turns off the low side gate drive output. The high side drive then turns on, restarting the switching cycle. The sync signal is inhibited when the controller operates in frequency foldback. The sync signal frequency must be greater than the maximum speci- fied free running frequency of the MIC2183. If the synchroniz- ing frequency is lower, double pulsing of the gate drive outputs will occur. When not used, the sync pin must be connected to ground. The maximum recommended output switching frequency is 600kHz. Synchronizing to higher frequencies may be pos- sible, however, higher power dissipation in the internal gate drive circuits will occur. The MOSFET gates require charge to turn on the device. The average current required by the MOSFET gate increases with switching frequency. Soft Start Soft start reduces the power supply input surge current at start up by controlling the output voltage risetime. The input surge appears while the output capacitance is charged up. A slower output risetime will draw a lower input surge current. Soft start may also be used for power supply sequencing. The soft start voltage is applied directly to the PWM compara- tor. A 5 µA internal current source is used to charge up the soft start capacitor. The capacitor is discharged when either the enable pin voltage drops below the standby threshold or the V DD voltage drops below its UVLO level. The part switches at a low duty cycle when the soft start pin voltage is zero. As the soft start voltage rises from 0V to 0.7V, the duty cycle increases from the minimum duty cycle to the operating duty cycle. The oscillator runs at the foldback frequency (1/4 of the switching frequency) until the feedback voltage rises above 0.3V. The risetime of the output is dependent of the soft start capacitor output capacitance, input and output voltage and load current. Voltage Setting Components The MIC2183 requires two resistors to set the output voltage as shown in Figure 5. VREF 1.245V Voltage Amplifier Pin 6 MIC2183 VOUT R1 R2 Figure 5 The output voltage is determined by the equation below. VV R R OUT REF =× + 1 1 2 Where: V REF for the MIC2183 is typically 1.245V. Lower values of R1 are preferred to prevent noise from appearing on the FB pin. A typically recommended value is 10k Ω. If R1 is too small in value it will decrease the efficiency of the power supply, especially at low output loads. Once R1 is selected, R2 can be calculated with the following formula. R VR VV REF OUT REF 2 1 = × – Efficiency Considerations Efficiency is the ratio of output power to input power. The difference is dissipated as heat in the buck converter. Under light output load, the significant contributors are: • The V INA supply current • The V INP supply current, which includes the current required to switch the external MOSFETs • Core losses in the output inductor To maximize efficiency at light loads: • Use a low gate charge MOSFET or use the smallest MOSFET, which is still adequate for maximum output current. • Use a ferrite material for the inductor core, which has less core loss than an MPP or iron power core. Under heavy output loads the significant contributors to power loss are (in approximate order of magnitude): • Resistive on time losses in the MOSFETs • Switching transition losses in the high side MOSFET • Inductor resistive losses • Current sense resistor losses • Input capacitor resistive losses (due to the capacitors ESR) To minimize power loss under heavy loads: • Use low on resistance MOSFETs. Use low threshold logic level MOSFETs when the input voltage is below 5V. Multiplying the gate charge by the on resistance gives a figure of merit, providing a good balance between low load and high load efficiency. • Slow transition times and oscillations on the voltage and current waveforms dissipate more power during the turn on and turn off of the MOSFETs. A clean layout will minimize parasitic inductance and capaci tance in the gate drive and high current paths. This will allow the fastest transition times and waveforms without oscillations. Low gate charge MOSFETs will transition faster than those with higher gate charge requirements. • For the same size inductor, a lower value will have fewer turns and therefore, lower winding resistance. However, using too small of a value will require more output capacitors to filter the output ripple, which will force a smaller bandwidth, slower transient response and possible instability under certain conditions. • Lowering the current sense resistor value will de crease the power dissipated in the resistor. However, it will also increase the overcurrent limit and will require larger MOSFETs and inductor components. • Use low ESR input capacitors to minimize the power dissipated in the capacitors ESR. |
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