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LP2992 Datasheet(PDF) 3 Page - Texas Instruments |
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LP2992 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 33 page ![]() LP2992 www.ti.com SNVS171H – NOVEMBER 2001 – REVISED JANUARY 2015 5 Pin Configuration and Functions SOT-23 (DBV) Package 5 Pins Top View WSON (NGD) Package 6 Pins Top View Pin Functions PIN I/O DESCRIPTION NAME DBV NAME NGD BYPASS 4 BYPASS 1 I Bypass capacitor for low-noise operation. GND 2 GND 2 – Ground. IN 1 IN 4 I Unregulated input voltage. – – N/C 5 – No internal connection. Connect to GND or leave open. A low voltage on this pin disables the device, and the regulator ON/OFF 3 ON/OFF 3 I enters a sleep mode. A high voltage on this pin enables the device. Regulated output voltage. This pin requires an output capacitor to OUT 5 OUT 6 O maintain stability. See the Detailed Design Procedure section for output capacitor details. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LP2992 |
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