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16F628 Datasheet(PDF) 165 Page - Microchip Technology |
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16F628 Datasheet(HTML) 165 Page - Microchip Technology |
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165 / 168 page  2002 Microchip Technology Inc. Preliminary DS40044A-page 163 PIC16F627A/628A/648A Q Q-Clock ............................................................................... 59 Quick-Turnaround-Production (QTP) Devices ...................... 7 R RC Oscillator ....................................................................... 96 RC Oscillator Mode Block Diagram............................................................. 96 Registers Maps PIC16F627A ................................................. 16, 17 PIC16F628A ................................................. 16, 17 Reset................................................................................... 97 RETFIE Instruction............................................................ 120 RETLW Instruction ............................................................ 121 RETURN Instruction ......................................................... 121 Revision History ................................................................ 155 RLF Instruction.................................................................. 121 RRF Instruction ................................................................. 122 S Serial Communication Interface (SCI) Module, See USART Serialized Quick-Turnaround-Production (SQTP) Devices ... 7 SLEEP Instruction ............................................................. 122 Software Simulator (MPLAB SIM)..................................... 126 Special Event Trigger. See Compare Special Features of the CPU .............................................. 93 Special Function Registers ................................................. 18 Status Register ................................................................... 22 SUBLW Instruction............................................................ 122 SUBWF Instruction ........................................................... 123 SWAPF Instruction............................................................ 123 T T1CKPS0 bit ....................................................................... 48 T1CKPS1 bit ....................................................................... 48 T1OSCEN bit ...................................................................... 48 T1SYNC bit ......................................................................... 48 T2CKPS0 bit ....................................................................... 53 T2CKPS1 bit ....................................................................... 53 Timer0 Block Diagrams Timer0/WDT ....................................................... 46 External Clock Input.................................................... 45 Interrupt....................................................................... 45 Prescaler..................................................................... 46 Switching Prescaler Assignment................................. 47 Timer0 Module ............................................................ 45 Timer1 Asynchronous Counter Mode ..................................... 50 Capacitor Selection ..................................................... 51 External Clock Input.................................................... 49 External Clock Input Timing ........................................ 50 Oscillator ..................................................................... 51 Prescaler............................................................... 49, 51 Resetting Timer1......................................................... 51 Resetting Timer1 Registers......................................... 51 Special Event Trigger (CCP)....................................... 57 Synchronized Counter Mode ...................................... 49 Timer Mode ................................................................. 49 TMR1H........................................................................ 50 TMR1L ........................................................................ 50 Timer2 Block Diagram............................................................. 52 Postscaler ................................................................... 52 PR2 register................................................................ 52 Prescaler .............................................................. 52, 59 Timer2 Module............................................................ 52 TMR2 output............................................................... 52 TMR2 to PR2 Match Interrupt..................................... 58 Timing Diagrams Timer0....................................................................... 143 Timer1....................................................................... 143 USART Asynchronous Receiver...................................... 80 USART Asynchronous Master Transmission ............. 77 USART Asynchronous Reception .............................. 80 USART RX Pin Sampling ..................................... 75, 76 USART Synchronous Reception ................................ 86 USART Synchronous Transmission ........................... 84 Timing Diagrams and Specifications ................................ 140 TMR0 Interrupt.................................................................. 105 TMR1CS bit ........................................................................ 48 TMR1ON bit........................................................................ 48 TMR2ON bit........................................................................ 53 TOUTPS0 bit ...................................................................... 53 TOUTPS1 bit ...................................................................... 53 TOUTPS2 bit ...................................................................... 53 TOUTPS3 bit ...................................................................... 53 TRIS Instruction ................................................................ 123 TRISA ................................................................................. 31 TRISB ................................................................................. 36 U Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................................. 69 Asynchronous Receiver Setting Up Reception.......................................... 82 Asynchronous Receiver Mode Address Detect ................................................... 82 Block Diagram .................................................... 82 USART Asynchronous Mode................................................... 76 Asynchronous Receiver.............................................. 79 Asynchronous Reception............................................ 81 Asynchronous Transmission....................................... 77 Asynchronous Transmitter.......................................... 76 Baud Rate Generator (BRG) ...................................... 71 Block Diagrams Transmit.............................................................. 77 USART Receive ................................................. 79 BRGH bit .................................................................... 71 Sampling......................................................... 72, 73, 74 Synchronous Master Mode......................................... 83 Synchronous Master Reception ................................. 85 Synchronous Master Transmission ............................ 83 Synchronous Slave Mode........................................... 86 Synchronous Slave Reception ................................... 87 Synchronous Slave Transmit...................................... 86 V Voltage Reference Configuration .............................................................. 67 Voltage Reference Module ......................................... 67 W Watchdog Timer (WDT).................................................... 106 WWW, On-Line Support ....................................................... 3 |
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