W949D6KB / W949D2KB

512Mb Mobile LPDDR

Publication Release Date: Dec. 11, 2014

Revision: A01-002

- 1 -

Table of Contents-

1. GENERAL DESCRIPTION .................................................................................................................................4

2. FEATURES ........................................................................................................................................................4

3. ORDER INFORMATION ....................................................................................................................................5

4. BALL CONFIGURATION....................................................................................................................................6

4.1

Ball Assignment: LPDDR x16 ...............................................................................................................6

4.2

Ball Assignment: LPDDR x32 ...............................................................................................................6

5. BALL DESCRIPTION .........................................................................................................................................7

5.1

Signal Descriptions...............................................................................................................................7

5.2

Addressing Table..................................................................................................................................8

6. BLOCK DIAGRAM..............................................................................................................................................9

6.1

Block Diagram ......................................................................................................................................9

6.2

Simplified State Diagram ....................................................................................................................10

7. FUNCTIONAL DESCRIPTION .........................................................................................................................11

7.1

Initialization.........................................................................................................................................11

7.1.1

Initialization Flow Diagram....................................................................................................12

7.1.2

Initialization Waveform Sequence ........................................................................................13

7.2

Mode Register Set Operation .............................................................................................................13

7.3

Mode Register Definition ....................................................................................................................14

7.3.1

Burst Length .........................................................................................................................14

7.3.2

Burst Definition .....................................................................................................................15

7.3.3

Burst Type ............................................................................................................................16

7.3.4

Read Latency .......................................................................................................................16

7.4

Extended Mode Register Description .................................................................................................16

7.4.1

Extended Mode Register Definition ......................................................................................17

7.4.2

Partial Array Self Refresh .....................................................................................................17

7.4.3

Automatic Temperature Compensated Self Refresh ............................................................17

7.4.4

Output Drive Strength...........................................................................................................17

7.5

Status Register Read .........................................................................................................................18

7.5.1

SRR Register Definition........................................................................................................18

7.5.2

Status Register Read Timing Diagram .................................................................................19

7.6

Commands .........................................................................................................................................20

7.6.1

Basic Timing Parameters for Commands .............................................................................20

7.6.2

Truth Table – Commands..................................................................................................20

7.6.3

Truth Table - DM Operations................................................................................................21

7.6.4

Truth Table – CKE.............................................................................................................21

7.6.5

Truth Table - Current State Bank n - Command to Bank n...................................................22

7.6.6

Truth Table - Current State Bank n, Command to Bank m ...................................................23

8. OPERATION ....................................................................................................................................................25

8.1

Deselect .............................................................................................................................................25

8.2

No Operation ......................................................................................................................................25

8.2.1

NOP Command ....................................................................................................................25

8.3

Mode Register Set..............................................................................................................................26

8.3.1

Mode Register Set Command ..............................................................................................26

8.3.2

Mode Register Set Command Timing...................................................................................26