ML2721 datasheet(15/27 Pages) MICRO-LINEAR

15 / 27 page

ML2721

January, 2000

PRELIMINARY DATASHEET

PRELIMINARY

The ~1MHz frequency shift is achieved by internally

adding an offset of +2 counts to the PLL divider register

value. The relationship between the LO frequency, the

programmed RF channel frequency, and the reference

frequency in RECEIVE mode is given in Table 6.

VCO OPEN AND CLOSED LOOP OPERATION

Normally the PLL is only operational in RXCAL and

TXCAL modes, when a closed loop PLL is formed. The PLL

is a conventional single loop integer division PLL. The

phase comparator has a charge pump output so that an

external passive loop filter can be used. The PLL dividers

support integer main divider ratios between 1024 and

4095, and reference divider ratios of 6 and 12.

In RECEIVE and TRANSMIT modes the PLL loop is opened

and the stored VCO tuning voltage (on the loop filter)

maintains the VCO at the desired frequency. In open loop

modes the PLL charge pump is shut off and the PLL

circuits are shut down to save power. Interlock logic

manages the start up and shut down of the PLL to ensure

that the VCO frequency is not disturbed in the transition

between modes. If better frequency stability is required

the RXCL bit in the PLL configuration register allows the

PLL to remain in the closed loop mode during RECEIVE

mode. The PLL loop must be opened in TRANSMIT mode,

as the PLL would otherwise attempt to remove the FM

transmit modulation.

PLL LOOP FILTER DESIGN

The PLL loop filter performs a dual function. In the closed

loop modes (RXCAL and TXCAL) it acts as a second order

loop filter, and in the open loop modes (TRANSMIT,

RECEIVE without RXCL) it holds the VCO tuning voltage

for the duration of the data slot. The correct loop filter

component values are a function of the desired closed

loop bandwidth, loop response damping factor charge

pump current, VCO tuning sensitivity and PLL division

ratio. The charge pump current, VCO tuning sensitivity,

and division ratio range are fixed by the on chip circuits,

so the only independent variables are the PLL’s closed

loop bandwidth and damping factor.

The recommended values of 47nF, 360

W and 3.3nF give a

50kHz closed loop bandwidth and a damping factor of 0.8

for robust closed loop operation. (18nF, 430

W and 1.8nF

reduce the damping factor to 0.72; 33nF, 390

W and 470pF

set the damping factor at 0.9). Plastic film capacitors are

used on the application circuit because of their excellent

MODE OF OPERATION (CONTINUED)

dielectric absorption and low leakage current. Ceramic

capacitors can be used, but care should be taken with

applications where there is significant thermal or

mechanical shock.

STANDBY MODE

In STANDBY the ML2721 transceiver is powered down.

The only active circuits are the control interfaces, which

are static CMOS to minimize power consumption. The

serial control interface (& control registers) remain

powered up and will accept and retain programming data

as long as the digital supply is present. The ML2721 serial

control registers should be loaded with control and

configuration data before any active mode is selected.

The filter alignment registers are reset at power up.

TEST MODE

Special test access circuitry is needed for IC production

test and radio debugging because of the RF to digital

functionality of the ML2721. Two analogue test outputs

(RXTPI and RXTPQ) are multiplexed with the RSSI and

lock detect (LD) output pins, and digital test outputs are

multiplexed onto the received data output pin (DOUT).

The test multiplexers are controlled by a test register

accessed over the serial control bus.

ML2721 Datasheet(PDF) 15 Page - Micro Linear Corporation

ML2721 Datasheet(HTML) 15 Page - Micro Linear Corporation

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