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ML2721 Datasheet(PDF) 17 Page - Micro Linear Corporation

Part # ML2721
Description  Low IF Digital Cordless Transceiver
PDF  27 Pages
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Manufacturer  MICRO-LINEAR [Micro Linear Corporation]
Direct Link  http://www.microlinear.com
Logo MICRO-LINEAR - Micro Linear Corporation

ML2721 Datasheet(HTML) 17 Page - Micro Linear Corporation

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ML2721
17
January, 2000
PRELIMINARY DATASHEET
PRELIMINARY
Table 8. Register Organization
CONTROL INTERFACES AND REGISTER DESCRIPTION (continued)
Register 0: PLL Configuration Register
14-bit Register Data
16-bit Register Data
2-bit Register Address
Res.
DB13
MSB
B15
DB12
B14
DB11
B13
DB10
B12
DB9
B11
DB8
B10
DB7
B9
DB6
B8
DB5
B7
DB4
B6
DB3
B5
DB2
B4
DB1
B3
DB0
B2
ADR1
B1
ADR0
B0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LOL
RCXL
RD0
QPP
0
0
Register 1: RF Channel Frequency Register
14-bit Register Data
16-bit Register Data
2-bit Register Address
Res.
DB13
MSB
B15
DB12
B14
DB11
B13
DB10
B12
DB9
B11
DB8
B10
DB7
B9
DB6
B8
DB5
B7
DB4
B6
DB3
B5
DB2
B4
DB1
B3
DB0
B2
ADR1
B1
ADR0
B0
Res.
CHQ11
CHQ10
CHQ9
CHQ8
CHQ7
CHQ6
CHQ5
CHQ4
CHQ3
CHQ2
CHQ1
CHQ0
0
1
Register 2: Filter Tuning Select and Text Mode Access Register
14-bit Register Data
16-bit Register Data
2-bit Register Address
TMODE
DB13
MSB
B15
DB12
B14
DB11
B13
DB10
B12
DB9
B11
DB8
B10
DB7
B9
DB6
B8
DB5
B7
DB4
B6
DB3
B5
DB2
B4
DB1
B3
DB0
B2
ADR1
B1
ADR0
B0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DTM2
DTM1
DTM0
ATM2
ATM1
ATM0
1
0
Register 3: Production Register (not for customer use)
Note: DB=Data Bit, ADR=Address Bit, Res.=Reserved.
14-bit Register Data
16-bit Register Data
2-bit Register Address
Res.
DB13
MSB
B15
DB12
B14
DB11
B13
DB10
B12
DB9
B11
DB8
B10
DB7
B9
DB6
B8
DB5
B7
DB4
B6
DB3
B5
DB2
B4
DB1
B3
DB0
B2
ADR1
B1
ADR0
B0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
1
REGISTER INFORMATION
A unidirectional three wire serial bus is used to set the
ML2721’s transceiver parameters and to program the PLL
circuits. Programming is performed by entering 16-bit
words into the ML2721 serial interface. Four 16-bit
registers are partitioned such that 14 bits are dedicated for
data to program the operation and 2 bits are used for
register addressing. Only three of the registers should be
used in normal operation. The purpose of each of the
registers is:
n Register 0: PLL configuration;
n Register 1: PLL tuning data;
n Register 2: Internal test access;
n Register 3: Reserved for production test only.
Table 8 shows a register map. Table 9 provides a detailed
diagram of the register organization: Table 9a and 9b
outline the PLL configuration and channel frequency
registers, and Table 9c displays the filter tuning and test
mode register.



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