ML6691

9

Reset: By setting this bit to a logic one, the Control register

will be reset to its default values. This bit self-clears upon

completion of the reset operation.

Loopback: By setting this bit to a logic one, the LPBK pin

will be held at a logic low. The COL signal will remain

low at all times, unless bit 7 is set, in which case the COL

signal shall behave as described.

Speed Selection: This bit is read-only and set at a logic

one by default.

Power Down: By setting this bit to a logic one, the

oscillator and all the MII input buffers except for MDIO

and MDC will be shut down.

Isolate: By setting this bit a logic one, the ML6691 can be

electrically isolated from the MII. In the isolation mode,

the input TXEN will be ignored and TXD[3:0] and TXER

shall not have any effect on the transmit section. All the

output buffers connected to the MII will be tri-stated. The

default state of this bit is determined by the LOCAL pin.

Duplex Mode: ML6691 will operate in Full Duplex mode

when this bit is set to a logic one. The COL signal will

remain low unless bit 7 is set.

Collision Test: By setting this bit to a logic one, the COL

signal will be asserted in response to the assertion of

TXEN, and will continue to assert the COL signal until

TXEN is deasserted.

STATUS REGISTER

Table 3 shows the applicable portions of the Status register

that are implemented in the ML6691. Bits 15, 12-3, 1, and

0 are read-only and have default values of logic low.

100BASE-TX Full Duplex

ML6691 can perform full duplex link transmission and

reception using the 100BASE-TX signaling specification.

This bit is always read as a logic one.

100BASE-TX Half Duplex

ML6691 can perform half duplex link transmission and

reception using the 100BASE-TX signaling specification.

This bit is always read as a logic one.

Link Status

When read as a logic one, this bit indicates that a valid

link has been established. The link status bit is

implemented with a latching function, such that the

occurrence of a link failure condition will cause the link

status bit to become cleared and remain cleared until it is

read via the management interface.

STATUS REGISTER

BIT

NAME

DESCRIPTION

R/W

14

100Base-TX

1 = able to perform full duplex

R/O

Full Duplex

0 = not able to perform full duplex

13

100Base-TX

1 = able to perform full duplex

R/O

Half Duplex

0 = not able to perform full duplex

2

Link Status

1 = link is up

R/O

0 = link is down

LL

NOTE:

R/O = Read Only,

LL = Latching Low

Table 3. Status Register