1

March 1997

ML6691

*

100BASE-T MII-to-PMD Transceiver

FEATURES

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Conforms to the Fast Ethernet 100BASE-T

IEEE 802.3

µ standard

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Integrated 4B/5B encoder/decoder

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Integrated Stream Cipher scrambler/descrambler

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Compliant MII interface

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Two-wire serial interface management port for

configuration and control

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On-chip 25 MHz crystal oscillator

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Interfaces to either AMD’s PDT/PDR (AM79865/79866)

or Motorola’s FCG (MC68836)

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Used with ML6673 for 100BASE-TX solutions

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44-pin PLCC package

GENERAL DESCRIPTION

The ML6691 implements the upper portion of the physical

layer for the Fast Ethernet 100BASE-T standard. Functions

contained in the ML6691 include a 4B/5B encoder/

decoder, a Stream Cipher scrambler/descrambler, and

collision detect. Additional functions of the ML6691 —

accessible through the two-wire MII management

interface — include full duplex operation, loopback,

power down mode, and MII isolation.

The ML6691 is designed to interface to a 100BASE-T

Ethernet Media Access Controller (MAC) via the MII

(Media Independent Interface) on one side, and a

100BASE-X PMD transceiver on the other side. A

complete 100BASE-TX physical layer (PHY) solution is

realized using the ML6691, the ML6673, and one of the

available clock recovery/generation devices. A 100BASE-

FX physical layer solution is implemented by disabling the

scrambler function of the ML6691 and using an external

* This Part Is End Of Life As Of August 1, 2000

optical PMD.

BLOCK DIAGRAM

OSC

NIBBLE

INPUT

REGISTER

4B/5B

ENCODER

STREAM

CIPHER

SCRAMBLER

SYMBOL

OUTPUT

REGISTER

TRANSMIT

STATE

MACHINE

COLLISION

DETECTION

RECEIVE

STATE

MACHINE

NIBBLE

OUTPUT

REGISTER

5B/4B

DECODER

SYMBOL

ALIGNER

STREAM

CIPHER

DESCRAMBLER

SYMBOL

INPUT

REGISTER

MANAGEMENT SECTION

CONTROL

STATUS

ISOLATE

FULLDUP

COLTST

LPBK

LINK FAILED

LOCAL

AD4...AD0

RST

MDIO

MDC

RXCLK

RXD3

RXD0

...

RXER

RXDV

CRS

COL

TXER

TXEN

TXCLK

TXD3

TXD0

...

TXC

GND

TSM4

TSM0

...

SD

DCFR

RXC

RSM4

RSM0

...

LPBK

CS