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KAI-2020 Datasheet(PDF) 21 Page - ON Semiconductor |
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KAI-2020 Datasheet(HTML) 21 Page - ON Semiconductor |
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21 / 37 page ![]() KAI−2020 www.onsemi.com 21 OPERATION Table 10. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Temperature TOP −50 70 °C 1 Humidity RH 5 90 % 2 Output Bias Current IOUT 0.0 10 mA 3 Off-Chip Load CL − 10 pF 4 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25°C. Excessive humidity will degrade MTTF. 3. Total for both outputs. Current is 5 mA for each output. Note that the current bias affects the amplifier bandwidth. 4. With total output load capacitance of CL = 10 pF between the outputs and AC ground. Table 11. MAXIMUM VOLTAGE RATINGS BETWEEN PINS Description Minimum Maximum Units Notes RL, RR, H1SL, H1SR, H2SL, H2SR, H1BL, H1BR, H2BL, H2BR, OGL, OGR to ESD 0 17 V Pin to Pin with ESD Protection −17 17 V 1 VDDL, VDDR to GND 0 25 V 1. Pins with ESD protection are: RL, RR, H1SL, H1SR, H2SL, H2SR, H1BL, H2BL, H1BR, H2BR, OGL and OGR. Table 12. DC BIAS OPERATING CONDITIONS (FOR < 40,000 ELECTRONS) Description Symbol Min. Nom. Max. Units Maximum DC Current Notes Output Gate OG −2.5 −2.0 −1.5 V 1 mA 4 Reset Drain RD 11.5 12.0 12.5 V 1 mA 5 Output Amplifier Supply VDD 14.5 15.0 15.5 V 1 mA 1 Ground GND 0.0 V Substrate SUB 8.0 VAB 17.0 V 3, 6 ESD Protection ESD −8.0 −7.0 −6.0 V 5 Output Amplifier Return VSS 0.0 0.7 1.0 V 1. One output, unloaded. 2. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The shipping container will be marked with two VAB voltages. One VAB will be for a 600 mV charge capacity (for operation of the horizontal clock frequencies greater than 20 MHz) and the other VAB will be for 1200 mV charge capacity (for horizontal clock frequencies at or below 20 MHz). 3. VESD must be at least 1 V more negative than H1L, H2L and RL during sensors operation AND during camera power turn on. 4. Output gate voltage must be set to –3 V for 40,000 − 80,000 electrons output in summed interlaced or binning modes. 5. Reset Drain voltage must be set to 13 V for 80,000 electrons output in summed interlaced or binning modes. 6. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. |
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