200 kHz

- 0.8 k:

LM5015

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SNVS538C – NOVEMBER 2007 – REVISED APRIL 2013

High Side Bootstrap Bias

The high side bootstrap bias provides power to drive the high side power MOSFET. An external capacitor is

required between the BST and the HO pins. A minimum capacitor value of 0.022 µF is recommended. The

capacitor is charged from VCC via an internal diode during each power MOSFET off-time.

Oscillator

A single external resistor connected between RT and AGND pins sets the LM5015 oscillator frequency. To set a

equation:

(1)

The tolerance of the external resistor and the frequency tolerance indicated in the Electrical Characteristics table

must be taken into account when determining the total variation of the switching frequency.

External Synchronization

The LM5015 can be synchronized to the rising edge of an external clock. Because the oscillator uses a divide-

Therefore, in order to synchronize, the external clock must have a frequency higher than twice the free running

peak voltage level greater than 3.2V at the RT pin is required for detection of the sync pulse. The DC voltage

synchronizing clock is clamped to 1.5V by an amplifier inside the LM5015 with approximately 100

Ω output

or greater to successfully synchronize the oscillator. The sync pulse width measured at the RT pin should have a

device and connected directly to the RT and AGND pins of the LM5015.

Enable / Standby

The LM5015 contains a dual level Enable circuit. When the EN pin voltage is below 0.45V, the IC is in a low

current shutdown mode with the VCC LDO disabled. When the EN pin voltage is raised above the 0.45V

shutdown threshold but below the 1.26V standby threshold, the VCC LDO regulator is enabled, while the

remainder of the IC is disabled. When the EN pin voltage is raised above the 1.26V standby threshold, all

functions are enabled and normal operation begins. An internal 6 µA current source pulls up the EN pin to

activate the IC when the EN pin is left disconnected.

An external set-point resistor divider from VIN to AGND can be used to determine the minimum operating input

voltage of the regulator. The divider must be designed such that the EN pin exceeds the 1.26V standby threshold

when VIN is in the desired operating range. The internal 6 µA current source should be included when

determining the resistor values. The shutdown and standby thresholds have 100 mV hysteresis to prevent noise

from toggling between modes. The EN pin is internally protected by a 6V Zener diode through a 1 k

Ω resistor.

The enabling voltage may exceed the Zener voltage, however the Zener current should be limited to less than 4

mA.

Error Amplifier and PWM Comparator

An internal high gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference. The output of the error amplifier is connected to the

COMP pin allowing the user to add loop compensation, typically a Type II network, as illustrated in Figure 15.

This network creates a pole at the origin that rolls off the high DC gain of the amplifier, which is necessary to

accurately regulate the output voltage. A zero provides phase boost near the open loop unity gain frequency, and

a high frequency pole attenuates switching noise. The PWM comparator compares the current sense signal from

the current sense amplifier to the error amplifier output voltage at the COMP pin.

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Product Folder Links: LM5015