HO

SR1

LO

SR2

T1

T2

T1

T2

Maximum Duty Cycle =

2

1

LM5035C

SNVS631C – JANUARY 2010 – REVISED MARCH 2013

www.ti.com

The HB and VCC capacitors should be placed close to the pins of the LM5035C to minimize voltage transients

due to parasitic inductances since the peak current sourced to the MOSFET gates can exceed 1.25A. The

recommended value of the HB capacitor is 0.01 µF or greater. A low ESR / ESL capacitor, such as a surface

mount ceramic, should be used to prevent voltage droop during the HO transitions.

The maximum duty cycle for each output is equal to or slightly less than 50% due to any programmed sync

rectifier delay. The programmed sync rectifier delay is determined by the DLY pin resistor. If the COMP pin is

open circuit, the outputs will operate at maximum duty cycle. The maximum duty cycle for each output can be

calculated with the following equation:

where

•

•

T1 is the programmed sync rectifier delay

(3)

programmed delay, the maximum duty cycle at this frequency is calculated to be 50%. Using a programmed sync

rectifier delay of 100 ns, the maximum duty cycle is reduced to 49%. Because there is no fixed dead-time in the

LM5035C, it is recommended that the delay pin resistor not be less than 10K. Internal delays, which are not

ensured, are the only protection against cross conduction if the programmed delay is zero, or very small.

Figure 17. HO, LO, SR1 and SR2 Timing Diagram

Synchronous Rectifier Control Outputs (SR1 & SR2)

Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low output

a MOSFET significantly reduces rectification losses. In a typical application, the transformer secondary winding is

center tapped, with the output power inductor in series with the center tap. The SR MOSFETs provide the ground

path for the energized secondary winding and the inductor current. Figure 17 shows that the SR2 MOSFET is

conducting while HO enables power transfer from the primary. The SR1 MOSFET must be disabled during this

period since the secondary winding connected to the SR1 MOSFET drain is twice the voltage of the center tap.

At the conclusion of the HO pulse, the inductor current continues to flow through the SR1 MOSFET body diode.

Since the body diode causes more loss than the SR MOSFET, efficiency can be improved by minimizing the T2

period while maintaining sufficient timing margin over all conditions (component tolerances, etc.) to prevent

shoot-through current. When LO enables power transfer from the primary, the SR1 MOSFET is enabled and the

SR2 MOSFET is off.

During the time that neither HO nor LO is active, the inductor current is shared between both the SR1 and SR2

MOSFETs which effectively shorts the transformer secondary and cancels the inductance in the windings. The

SR2 MOSFET is disabled before LO delivers power to the secondary to prevent power being shunted to ground.

The SR2 MOSFET body diode continues to carry about half the inductor current until the primary power raises

the SR2 MOSFET drain voltage and reverse biases the body diode. Ideally, dead-time T1 would be set to the

minimum time that allows the SR MOSFET to turn off before the SR MOSFET body diode starts conducting.

16

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