LM5035C

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SNVS631C – JANUARY 2010 – REVISED MARCH 2013

The SR1 and SR2 outputs are powered directly by the 5V ref regulator. Each output is capable of sourcing 0.09A

and sinking 0.2A peak. The SR1 and SR2 signals can control SR MOSFET gate drivers through a digital isolator.

The actual gate sourcing and sinking currents are provided by the secondary-side bias supply and gate drivers.

The timing of SR1 and SR2 with respect to HO and LO is shown in Figure 17. SR1 is configured out of phase

with HO and SR2 is configured out of phase with LO. The deadtime between transitions is programmable by a

deadtime periods can be calculated using the following formulae:

(4)

(5)

When UVLO falls below 1.25V, or during hiccup current limit, both SR1 and SR2 are held low. During normal

operation, if soft-start is held low, both SR1 and SR2 will be high.

Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated

junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power

standby state with the output drivers (HO, LO, SR1 and SR2), the bias regulators (VCC and REF) disabled. This

helps to prevent catastrophic failures from accidental device overheating. During thermal shutdown, the soft-start

capacitor is fully discharged and the controller follows a normal start-up sequence after the junction temperature

falls to the operating level (145°C).

APPLICATIONS INFORMATION

The following information is intended to provide guidelines for the power supply designer using the LM5035C.

VIN

The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power

gate charge provided to the output drivers, the switching frequency, and any external loads on the VCC and REF

pins. It is recommended the filter shown in Figure 18 be used to suppress transients which may occur at the

input supply. This is particularly important when VIN is operated close to the maximum operating rating of the

LM5035C.

When power is applied to VIN and the UVLO pin voltage is greater than 0.4V, the VCC regulator is enabled and

supplies current into an external capacitor connected to the VCC pin. When the voltage on the VCC pin reaches

the regulation point of 7.6V, the voltage reference (REF) is enabled. The reference regulation set point is 5V. The

HO, LO, SR1 and SR2 outputs are enabled when the two bias regulators reach their set point and the UVLO pin

potential is greater than 1.25V. In typical applications, an auxiliary transformer winding is connected through a

diode to the VCC pin. This winding must raise the VCC voltage above 8.3V to shut off the internal start-up

regulator.

After the outputs are enabled and the external VCC supply voltage has begun supplying power to the IC, the

current into VIN drops below 1 mA. VIN should remain at a voltage equal to or above the VCC voltage to avoid

reverse current through protection diodes.

For Applications >100v

For applications where the system input voltage exceeds 100V or the IC power dissipation is of concern, the

LM5035C can be powered from an external start-up regulator as shown in Figure 19. In this configuration, the

VIN and the VCC pins should be connected together, which allows the LM5035C to be operated below 13V. The

voltage at the VCC pin must be greater than 8.3V yet not exceed 15V. An auxiliary winding can be used to

reduce the power dissipation in the external regulator once the power converter is active. The NPN base-emitter

reverse breakdown voltage, which can be as low as 5V for some transistors, should be considered when

selecting the transistor.

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