A25LS512A datasheet(17/43 Pages) AMICC

17 / 43 page

A25LS512A Series

(November, 2014, Version 1.1)

AMIC Technology Corp.

Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the

Fast_Read (0Bh) instruction except the data is output on two

pins, DO and DIO, instead of just DO. This allows data to be

transferred from the A25LS512A at twice the rate of standard

SPI devices.

Similar to the Fast Read instruction, the Fast Read Dual

Output instruction can operate at the highest possible

frequency

fC (See AC Characteristics). This is

accomplished by adding eight “dummy” clocks after the

24-bit address as shown in figure 10. The dummy clocks

allow the device’s internal circuits additional time for setting

up the initial address. The input data during the dummy

clocks is “don’t care”. However, the DIO pin should be

high-impedance prior to the falling edge of the first data out

clock.

Figure 10. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence

Instruction

High Impedance

MSB

810

01 2 3 4 5 6 7

24-Bit Address

28 29 30 31

23 22 21

3 21 0

DIO

32 33 34 35 36 37 38 39

654

40 41 42 43 44 45 46 47

Dummy Byte

MSB

7 5 31 75 3

MSB

7 5 31 75 3 1

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Data Out 1

Data Out 2

Data Out 3

Data Out 4

DIO switches from input to output

Note: Address bits A23 to A16 are Don’t Care, for A25LS512A.

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