LP62S161024 Series

PRELIMINARY

(November, 2014, Version 0.0)

8

AMIC Technology, Corp.

Symbol

Parameter

LP62S161024-55LL(I)

LP62S161024-70LL(I)

Unit

Max.

Min.

Min.

Max.

Read Cycle

Read Cycle Time

55

-

70

-

ns

Address Access Time

-

55

-

70

ns

Chip Enable Access Time

-

55

-

70

ns

Byte Enable Access Time

-

55

-

70

ns

Output Enable to Output Valid

-

25

-

35

ns

Chip Enable to Output in Low Z

10

-

10

-

ns

Byte Enable to Output in Low Z

10

-

10

-

ns

Output Enable to Output in Low Z

5

-

5

-

ns

Chip Disable to Output in High Z

-

20

-

25

ns

Byte Disable to Output in High Z

-

20

-

25

ns

Output Disable to Output in High Z

-

20

-

25

ns

Output Hold from Address Change

5

-

5

-

ns

Write Cycle

Write Cycle Time

55

-

70

-

ns

Chip Enable to End of Write

50

-

60

-

ns

Byte Enable to End of Write

50

-

60

-

ns

Address Setup Time

0

-

0

-

ns

Address Valid to End of Write

50

-

60

-

ns

Write Pulse Width

40

-

50

-

ns

Write Recovery Time

0

-

0

-

ns

Write to Output in High Z

-

25

-

25

ns

Data to Write Time Overlap

25

-

30

-

ns

Data Hold from Write Time

0

-

0

-

ns

Output Active from End of Write

5

-

5

-

ns

circuit condition and are not referred to output voltage levels.