LP62S161024 datasheet(12/16 Pages) AMICC

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LP62S161024 Datasheet(PDF) 12 Page - AMIC Technology

Part #	LP62S161024

Description	16M BIT (1M x 16 / 2M x 8) LOW VOLTAGE CMOS SRAM

PDF	16 Pages

Scroll/Zoom	100%

Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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12 / 16 page

LP62S161024 Series

PRELIMINARY

(November, 2014, Version 0.0)

AMIC Technology, Corp.

Timing Waveforms (continued)

Write Cycle 3

(Byte Enable Controlled)

tWC

tAW

Address

CS1

tWR3

tCW1 , tCW2

tBW2

tAS1

DATA IN

DATA OUT

HB, LB

tWP

tDW

tDH

tOW

tWHZ4

CS2

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP, tBW) of a low

CS , WE and ( HB and , or LB ) or a high CS2.

3. tWR is measured from the earliest of

or WE or ( HB and , or LB ) going high or CS2 going Low to the end of the

Write cycle.

4. OE level is high or low.

5. Transition is measured

±500mV from steady state. This parameter is sampled and not 100% tested.

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