LX1570/1571

PRODUCT DA T ABOOK 1996/1997

7

Copyright © 1997

Rev. 0.9.3

1/97

IC DESCRIPTION

STEADY-STATE OPERATION

Steady-state operation is best described by referring to the main

block diagram and the typical application circuit shown in Fig-

ure 2. The output drive turns the external power MOSFET on

and current ramps up in the inductor. Inductor current is sensed

with an external resistor (or in the case of LX1571 with a current

transformer) and is compared to the threshold at the inverting

input of the current sense (C.S.) comparator. This threshold is

set by the voltage feedback loop, which is controlled by the

error amplifier. Exceeding this threshold resets the PWM latch

and turns the MOSFET off. The Output drive goes low, turning

the C

ing the C

1.5V, it sets the PWM latch and turns the output drive back on

prior to the next rising edge of the transformer voltage, and the

cycle repeats.

The Steady-State Operation Timing Diagram - Normal Mode

(Figure 4A) shows typical waveforms in the steady-state condi-

tion. Notice that when the current sense signal turns the MOSFET

off, it also synchronizes the output drive to the transformer volt-

age (see discussion under heading Timing Section). In addition,

the energy transfer occurs only when both transformer voltage

and OUT DRV pin are "HI" at the same time, establishing the

effective on-time of the converter. This shows that the regula-

tion of this converter is achieved by modulating the trailing edge

of the output drive with respect to the leading edge of the AC

voltage, while maintaining a fixed output drive duty cycle. In

other words, the converter duty cycle seen by L1 is controlled by

varying the phase between the AC voltage and the output driver

signal (phase modulation). Maximum converter duty cycle is

achieved when both signals are in phase, as shown in Figure 4B.

The LX1570/71 output drive always maintains a fixed duty cycle

(

≈54%), since both charge and discharge currents are almost equal

as shown in Figures 4A and 4B.

Error Amp

2.5V

C.S. Comp

R

S

Q

PWM Latch

7

6

V

CC

OUT DRV

R

Internal

Bias

2.5V

REF

1V

5V

2.5V

4

3

2

1

S.S.

V

FB

COMP

C.S.

8

C

T

Timing / Duty Cycle

Control

CHG

CONTROL

LATCH

SET CONTROL

DISCH

CONTROL

FIGURE 3 — STEADY-STATE OPERATION BLOCK DIAGRAM