SM5170AV

NIPPON PRECISION CIRCUITS—5

FUNCTIONAL DESCRIPTION

Frequency Divider Data

The input data should be specified keeping in mind

DATA and LE pins into the shift register and latch

ply level, however, is not needed and can be ON or

OFF.

The control data input uses a 3-line 24-bit serial

interface comprising the clock (CLK), data input

(DATA) and latch enable (LE). The data is input with

the MSB first. The last two bits (23rd + 24th) are

used as the latch select control bits. Data is written to

the shift register on the rising edge of the clock sig-

nal. Accordingly, the data should change state on the

falling edge of the clock signal. Data is transferred

from the shift register to the latch when the latch

enable (LE) signal goes HIGH. Accordingly, the

latch enable signal should be held LOW while data is

being written to the shift register.

The clock and data input signals are both ignored

when the latch enable signal goes HIGH. Also, the

CLK, DATA and LE inputs should be tied LOW

when not setting data.

Input Data Description

Latch select

The last two data bits determine the status of the shift register data latch.

FIN input frequency Divider (N-counter) Structure

The FIN input frequency divider generates a compar-

ator frequency signal (FV), which is input to the

phase comparator, by dividing the VCO signal input

on pin FIN.

The phase comparator is comprised of dual modulus

prescalers, a 5-bit swallow counter and a 12-bit main

counter.

Figure 1. Frequency divider data format

12

345

678

9

10

11

12

13

14

15

16

17

MSB

CLK

DATA

LE

18

19

20

21

22

23

LSB

Control bits

24

Figure 2. Latch select data format

Bit 23

Bit 24

Latch

00

S w allow counter and main counter frequency

divider ratio latch select

01

Reference frequency counter divider ratio

data and LD output latch select

12

345

678

9

10

11

12

13

14

15

16

17

MSB

DATA

18

19

20

21

22

23

LSB

Control bits

24

Frequency settings

Prescaler

P and P + 1

Swallow counter

S

Main counter

M

FIN input frequency divider ratio

N = (P + 1)

× S + P × (M − S)

× M + S (where M > S)

Counter set ranges

Prescaler

P = 32, P + 1 = 33

Swallow counter

S = 0 to 31

Main counter

M = 32 to 4095

FIN input frequency divider ratio range

N = 1056 to 131071