12

ACE9040

ELECTRICAL CHARACTERISTICS

These characteristics are guaranteed over the following conditions unless otherwise stated (Note 1):

T

Fig.3a Serial Interface Input Timing

Characteristic

Symbol

Value

Unit

Conditions

Min.

Typ.

Max.

DC Characteristics

Logic input high

V

IH

0.7 x V

DD

V

V

Logic input low

V

IL

- 0.3

0.3 x V

DD

V

Input Capacitance

C

in

10

pF

logic inputs leakage current

I

ILK

± 1

µA

SCLK, SD, LEN inputs

V

AC Characteristics

Clock input frequency: Serial

f

CLK

1.008

MHz

interface & SC Filters

-100

100

ppm

Deviation from 1.008 MHz

Clock duty cycle

D

40

50

60

%

Number of clock rising edges to

24

clock

input data

cycles

Clock cycles between latch pulses

30

clock

on LEN

cycles

Clock cycles before power-up and

8

clock

after powerdown

cycles

Data setup time

t

ds

80

ns

V

Data hold time

t

dh

80

ns

T

Clock low

t

cll

400

600

ns

Clock high

t

clh

400

600

ns

Clock high to latch high

t

cl

440

ns

Latch high to clock high

t

lc

220

ns

Latch high

t

lh

240

ns

Rise and fall times

50

ns

All digital inputs

Power Supply Rejection Ratio:

PSRR

V

COMP[2:1] = 00.

TX path (LI to TLPO)

– 12

dB

LI = 0 dB, V485 = 13.5 dB

INPSENSE = 0 dB, softlimit on.

RX path (RXI to EPOP)

– 20

dB

AUDIODEV, RXSENSE = 0 dB

THF, RHF, EARSENSE = 0 dB

RXV, SIDETONE off.

Crosstalk TX to RX

-45

dB

MOD = 0.2 V

RMS

(MOD to EPOP/EPON)

SCLK

Data

Latch