ACE9040 datasheet(15/33 Pages) MITEL

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ACE9040

DESCRIPTION

the control bits for one of the standards are set, others are

under user control.

Power saving operates when an individual block is de-

selected and for the whole circuit when in Standby. The circuit

combines high performance with minimum power

consumption and uses as few external components as

possible.

SERIAL CONTROL BUS

All functions are controlled via a three wire serial

interface. Input is via pins SD for serial data, SCLK for the clock

input and LEN for the control message latch signal.

Incoming data bits are clocked in on the rising edges of

SCLK clock input. At the end of each control message

comprising three 8-bit data bytes, the rising edge of the LEN

pulse latches in the data. A system controller should clock

data out on clock falling edges to ensure the maximum timing

margins.

The SCLK clock input must be at 1·008 MHz and

continuous whenever the ACE9040 is active because

ACE9040’s switched capacitor filters use clocks derived from

SCLK to set frequency responses.

ACE9040 expects a minimum of 30 clock cycles between

LEN latch pulses, including the clock cycle containing the latch

pulse. A minimum of 8 clock cycles before the beginning of an

Operate command or after a Standby command are expected.

Three data bytes DATA1, DATA2, and DATA3 contain

bits for system selection, control and mute switches, gain

control and filter response settings, as shown in figure 10. The

last two bits of DATA3, DATA3[1] and [0], determine the

message type, either “Operation”, “Initializing mode 0”,

“Initializing mode 1” or “Handsfree”. The details of these four

modes are described in tables 2 to 19.

ACE9040 combines all the voice, data and signalling

processing circuits for analog cellular telephones operating

with the AMPS or TACS systems.

Transmit channel functions comprise a microphone

amplifier, soft limiter, bandpass speech filter, compressor,

pre-emphasis filter, hard limiter, lowpass transmit filter and a

gain control stage to set the deviation. Additional transmit

circuits include a DTMF generator, a lowpass filter for either

control data or signalling tone (ST), filters for supervisory

audio tone (SAT), either transponded or locally re-generated,

and deviation setting amplifiers for Data, ST and SAT. The

outputs from the transmit functions feed a modulation

combiner whose gain can be adjusted before driving a

modulator and external power amplifier.

ACE9040’s receive path consists of a bandpass filter,

expander, volume control and power amplifier to directly drive

the earpiece, either differentially or in single ended modes.

Sidetone and DTMF tones can be introduced into the receive

path.

Gain settings, filter characteristics and system control is

programmed via a three wire serial interface to give optimum

operation with either the AMPS or TACS analog cellular

systems.

To implement a handsfree function, both transmit and

receive paths have rectifiers which enable signal amplitude

monitoring via an external pin and signal path attenuators

controlled via the serial interface.

All filter characteristics are set by ratioed on-chip

components and by a fixed externally input clock rate of

1·008 MHz and do not need trimming, filter response options

are selected via the serial interface.

Gain adjustments for different system specifications and

component tolerancing are set via the serial interface using

gain control blocks in the transmit and receive signal paths.

These eliminate the need for any mechanically adjusted

potentiometers. Some gain levels change automatically when

DATA3[1]

DATA3[0]

Mode

“Operation”

“Initializing mode 0”

“Initializing mode 1”

“Handsfree”

Fig. 10 Serial Receive Bus Timing

Table 1 Mode Selections

DATA1

DATA2

DATA3

SCLK

LEN

765432107654321076543210

EARLIEST

START OF

MESSAGE

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