4-34

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

20 24 28

1

1

1

IN+

Non-inverting op-amp input.

2

2

2

IN-

Inverting op-amp input.

334

GS

Gain Select. Gives access to output of front end differential amplifier for connection of

feedback resistor.

557

6

6

8

OSC1 DTMF clock/oscillator input.

7

7

9

OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the

internal oscillator circuit. Leave open circuit when OSC1 is clock input.

810 12 TONE Tone output (DTMF or single tone).

911 13

R/W Read/Write input. Controls the direction of data transfer to and from the MPU and the

transceiver registers. TTL compatible.

10 12 14

CS

Chip Select, TTL input (CS=0 to select the chip).

11 13 15

RS0 Register Select input. See register decode table. TTL compatible.

12 14 17

Φ2 System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the

device is not being accessed.

13 15 18

IRQ/

CP

Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has

been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal

representative of the input signal applied at the input op-amp. The input signal must be within

the bandwidth limits of the call progress filter. See Figure 8.

14-

17

18-

21

19-

22

D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or

Φ2 is low.

18 22 26

ESt

Early Steering output. Presents a logic high once the digital algorithm has detected a valid

tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to

a logic low.

causes the device to register the detected tone pair and update the output latch. A voltage

external steering time-constant; its state is a function of ESt and the voltage on St.

20 24 28

8,9

16,

17

3,5,

10,

11,

16,

23-

25

NC

No Connection.

1

2

3

4

5

6

7

8

9

10

11

12

20

19

18

17

16

15

14

13

IN+

IN-

GS

VRef

VSS

OSC1

OSC2

TONE

R/W

CS

VDD

St/GT

ESt

D3

D2

D1

D0

IRQ/CP

Φ2

RS0

20 PIN CERDIP/PLASTIC DIP/SOIC

28 PIN PLCC

5

6

7

8

9

10

11

25

24

23

22

21

20

19

•

NC

VRef

VSS

OSC1

OSC2

NC

NC

NC

NC

NC

D3

D2

D1

D0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

24

23

22

21

20

19

18

17

IN+

IN-

GS

VRef

VSS

OSC1

OSC2

NC

TONE

R/W

CS

VDD

St/GT

ESt

D3

D2

D1

D0

NC

NC

NC

IRQ/CP

Φ2

RS0

24 PIN SSOP