MT8926AP datasheet(17/26 Pages) MITEL

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4-19

MT8926

Applications

Figure 9 illustrates a typical application of a MT8926

PMAC. T1 data is transmitted and received using a

generic Line Interface Unit (LIU). The LIU passes the

received data and extracted clock to both the

MT8926 and MT8976. E8Ko (MT8976) is derived

from E1.5i by dividing it by 193 and aligning the

result with the receive framing. E8Ko (MT8976)

connects to E8Ki (MT8926), and is used by the

MT8926 for frame alignment. E8Ko (MT8926) is

connected to C8Kb of the MT8941. In MT8941

normal mode, C8Kb is the reference clock for the ST-

BUS and transmit signals (F0, C4 and C2). This 8

kHz output can be turned off (output high) at the

MT8926 so the MT8941 reference clock can be

derived from another interface. The intrinsic jitter

(typical 0.07 UI) and jitter attenuation of the MT8941

will meet T1.408 requirements (see MT8941 data

sheet).

Control of the MT8926 is accomplished over the

CSTi1 ST-BUS stream, which is shared by the

MT8926 and MT8976. Status data (Performance

Monitoring Information) is inserted into the MT8976

CSTo stream by the MT8926 and is output on its

CSTo stream. This CSTo stream data is routed

through the MT8980 switch, in message mode, to the

microprocessor. The microprocessor will assemble

the

information

section

the

T1.403/T1.408

message-oriented signal and pass it to the MT8952

HDLC controller for transmission over the facility

data link. The MT8952 must be in external timing

mode and will be clocked by the RxFDLCLK output

to the MT8976. The assembly and transmission of

the message-oriented signal is under control of the

1SEC output of the MT8926.

Bit-oriented messages are also transmitted and

received via MT8980 message mode access to the

CSTi1 and CSTo streams. The MT8926 will receive

bit-oriented messages from the receive T1 line (i.e.,

RxA and RxB). Both bit-oriented and message-

oriented signals are transmitted over the MT8926

FDLo to MT8976 TxFDL link.

Payload

loopback

performed

internally

connecting DSTi1 to DSTo of the MT8926 (under

control of the CSTi1 stream), instead of the normal

connection of DSTi0 to DSTo (see Figure 6).

IRQ is an open drain interrupt output that will signal

the microprocessor when an exception condition

occurs (see Figure 8). Exception conditions are

Figure 9 - Typical T1.403/T1.408 Application

From

other

interfaces

To/From

other

interfaces

Performance

Monitoring

Message/

Data

Storage

CDSTo

CDSTi

CKi

T1.403/T1.408

Message-Oriented

Signal Control

INT0

INT1

µP

MT8952

MT8926

MT8941

MT8976

4.7k

Ω

VDD

STi2

STo3

•

STo7

STi7

C4i

F0i

STo0

STo1

STi0

STo2

STi1

•

••

16.384

MHz

Osc.

C8Kb

C4b C2o F0b

F0i CVb

12.352

MHz

Osc.

To other T1

Interfaces

Line

Interface

Unit

(LIU)

RxA

RxB

E1 5i

F0i

C2i

CSTi1

E8Ko

CSTo

TxFDL

DSTi

DSTo

CSTi0

RxFDL

RxFDLCLK

TxFDLCLK

RxSF

TxSF

XCtl

C1.5i

TxA

TxB

RxA

RxB

ECLK

F0i

C2i

CSTi1

E8Ki

CSTi0

FDLo

DSTo

E8Ko

CSTo

DSTi0

DSTi1

IRQ

1SEC

FDLi

To other

Interfaces

Receive

Transmit

}

MT8980

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