4-4

MT8926

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

System Ground.

2ECLK

Extracted Clock Input. A 1.544 MHz clock derived from the received data. This signal is

used to clock in the data on pins RxA and RxB.

See Figure 11 for timing information.

3RxA

Receive A Input. A unipolar active low signal decoded from the received T1 signal. See

Figure 11 for timing information.

4RxB

Receive B Input. A unipolar active low signal decoded from the received T1 signal. See

Figure 11 for timing information.

5IC

6E8Ki

Extracted 8 kHz Input. A low going pulse on this input is used by the PMAC to locate the

framing bit in the received signal. The device uses this information to detect errors in the

received framing bits. Connect to E8Ko of the MT8976/77. See Figure 12 for timing

information.

7E8Ko

8 kHz clock output. The 8 kHz signal input at E8Ki is output on this pin when bit 2 (8KEn)

of the PMAC Control Word is set. The output is pulled high when 8KEn is reset. See

Figure 12 for timing information.

System Ground.

9

CSTo

Control ST-BUS Output. The data that enters the PMAC on CSTi0 will exit the device on

this pin. Data derived by the PMAC will be inserted into specific channels of this output

stream. See Figures 13 and 14 for timing information and Figure 5 for channel allocation.

10

CSTi0

Control ST-BUS Input 0. Accepts the serial ST-BUS stream output on CSTo of the

MT8976/77. The data that enters the PMAC on this pin exits the device on CSTo. The

contents of specific CSTi0 channels is replaced by data derived by the PMAC. See Figures

13 and 14 for timing information and Figure 4 for channel allocation.

11

CSTi1

Control ST-BUS Input 1. Channel 11 of this ST-BUS input stream is used to control

specific features in the device (Table 14). Channel 7 is used for the transmit bit-oriented

message (Table 13), and channel 15 is used to control loopback functions (Table 4). See

Figure 13 for timing information and Figure 3 for channel allocation.

12

F0i

Frame Pulse Input. This input accepts an 8 kHz signal, which is used to delineate the ST-

BUS frame boundary. See Figure 15 for timing information.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

28

27

26

25

24

23

22

21

28 PIN PLASTIC DIP

VSS

ECLK

RxA

RxB

IC

E8Ki

E8Ko

VSS

CSTo

CSTi0

CSTi1

F0i

C2i

VSS

VDD

IC

DSTi1

DSTi0

DSTo

IC

VSS

IC

IRQ

1SEC

FDLo

FLDi

RESET

VDD

1

6

5

43

2

7

8

9

10

11

23

19

20

21

22

24

25

26

27

28

12 13 14 15 16 17 18

DSTi0

DSTo

IC

VSS

IC

IRQ

1SEC

IC

E8Ki

E8Ko

VSS

CSTo

CSTi0

CSTi1

28 PIN PLASTIC J-LEAD