MT8940 datasheet(13/16 Pages) MITEL

13 / 16 page

ISO-CMOS

MT8940

3-39

† Timing is over recommended temperature & power supply voltages.

‡ Typical ﬁgures are at 25

°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output

AC Electrical Characteristics†-Voltages are with respect to ground (V

SS) unless otherwise stated.(Ref. Figures 11&12)

Characteristics

Sym

Min

Typ‡

Max

Units

Test Conditions

C4b output delay (HIGH to

LOW) from C8Kb input/output

t84H

-25

Test load circuit 2 (Fig. 17)

on C8Kb.

C4b output clock period

tP4o

240

282

Test load circuit 1 (Fig. 17).

C4b output clock width (HIGH)

tW4oH

123

165

C4b output clock width (LOW)

tW4oL

110

123

C4b output clock rise time

trC4

Test load circuit 1 (Fig. 17).

C4b clock output fall time

tfC4

Test load circuit 1 (Fig. 17).

Frame pulse output delay

(HIGH to LOW) from C4b

tFPL

Test load circuit 1 (Fig. 17).

Frame pulse output delay

(LOW to HIGH) from C4b

tFPH

Test load circuit 1 (Fig. 17).

Frame pulse (F0b) width

tWFP

200

245

C4o delay - LOW to HIGH

t4oLH

C4o delay - HIGH to LOW

t4oHL

C4b to C2o delay (LOW to

HIGH)

t42LH

-10

+10

C4b to C2o delay (HIGH to

LOW)

t42HL

C2o clock period

tP2o

486

523

Test load circuit 1 (Fig. 10).

C2o clock width (HIGH)

tW2oH

244

291

C2o clock width (LOW)

tW2oL

233

244

C2o clock rise time

trC2

Test load circuit 1 (Fig. 10).

C2o clock fall time

tfC2

Test load circuit 1 (Fig. 10).

C2o delay - LOW to HIGH

t2oLH

C2o delay - HIGH to LOW

t2oHL

-5

VOH

VOL

VOH

VOL

VOH

VOL

VIH

VIL

C4b

F0b

C8Kb

Output

C8Kb

Input

t84H

tW4oH

tP4o

tFPL

tFPH

tW4oL

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