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MT8940 Datasheet(PDF) 2 Page - Mitel Networks Corporation |
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MT8940 Datasheet(HTML) 2 Page - Mitel Networks Corporation |
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2 / 16 page ![]() MT8940 ISO-CMOS 3-28 Figure 2 - Pin Connections Pin Description Pin # Name Description 1ENCV Variable clock enable (TTL compatible input) - This input (pulled internally to VDD) directly controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1 is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input. 2 MS0 Mode select ‘0’ input (TTL compatible) - This input (pulled internally to VSS) in conjunction with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2). 3 C12i Clock 12.355 MHz input (TTL compatible) - Master clock input at 12.355 MHz ±100ppm for DPLL #1. 4 MS1 Mode select-1 input (TTL compatible) - This input (pulled internally to VSS) in conjunction with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2) 5 F0i Frame pulse input (TTL compatible) - This is the frame pulse input (pulled internally to VDD) at 8 kHz. The DPLL #1 locks to the falling edge of this input to generate T1 (1.544 MHz) clock. 6 F0b Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending on the minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts as an input (pulled internally to VDD) to an external frame pulse. 7 MS2 Mode select-2 input (TTL compatible) - This input (pulled internally to VDD) in conjunction with MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.) 8 C16i Clock 16.388 MHz input (TTL compatible) - Master clock input at 16.388 MHz ±32 ppm for DPLL #2. 9ENC4o Enable 4.096 MHz clock (TTL compatible input) - This active high input (pulled internally to VDD) enables C4o (pin 11) output. When LOW, the output C4o is in high impedance condition. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 ENVC MS0 C12i MS1 F0i F0b MS2 C16i ENC4o C8Kb C4o VSS VDD RST CV CVb Yo Bi Ai MS3 ENC2o C2o C2o C4b |
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