MT89L85AP datasheet(5/20 Pages) MITEL

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Advance Information

MT89L85

2-5

Variable Delay mode

The delay in this mode is dependent only on the

combination of source and destination channels and

it is not dependent on the input and output streams.

The minimum delay achievable in the MT89L85

device is 3 time slots. In the MT89L85 device, the

information that is to be output in the same channel

position as the information is input (position n),

relative to frame pulse, will be output in the following

frame (channel n, frame n+1). The same occurs if

the input channel has to be output in the two

channels succeeding (n+1 and n+2) the channel

position as the information is input.

The information switched to the third timeslot after

the input has entered the device (for instance, input

channel 0 to output channel 3 or input channel 30 to

output channel 1), is always output three channels

later.

Any switching conﬁguration that provides three or

more timeslots between input and output channels,

will have a throughput delay equal to the difference

between the output and input channels; i.e., the

throughput delay will be less than one frame. Table 1

shows the possible delays for the MT89L85 device in

Variable Delay mode:

Table 1 - Channel Delay for the Variable Delay

Mode

Constant Delay Mode

In this mode frame integrity is maintained in all

switching conﬁgurations by making use of a multiple

Data-Memory buffer technique where input channels

written in any of the buffers during frame N will be

read out during frame N+2. In the MT89L85, the

minimum throughput delay achieve-able in Constant

Delay mode will be 32 time slots; for example, when

input time slot 32 (channel 31) is switched to output

time slot 1 (channel 0). Likewise, the maximum delay

is achieved when the ﬁrst time slot in a frame

(channel 0) is switched to the last time slot in the

frame (channel 31), resulting in 94 time slots of

delay.

Input

Channel

Output

Channel

Throughput Delay

m=n, n+1 or

n+2

m-n + 32 timeslots

m>n+2

m-n time slots

m<n

32-(n-m) time slots

To summarize, any input time slot from input frame N

will be always switched to the destination time slot on

output frame N+2. In Constant Delay mode, the

device throughput delay is calculated according to

the following formula:

DELAY = [32 + (32 - IN) + (OUT - 1)];

(expressed in number of time slots)

Where:

IN is the number of the input time slot

(from 1 to 32).

OUT is the number of the output time slot

(from 1 to 32).

Microprocessor Port

The

MT89L85

microprocessor

port

has

compatibility

with

Mitel

MT8985

Digital

Switch

devices providing a non-multiplexed bus architecture.

The parallel port consists of an 8 bit parallel data bus

(D0-D7), six address input lines (A0-A5) and four

control lines (CS, DS, R/W and DTA). This parallel

microport allows the access to the Control registers,

Connection Memory High, Connection Memory Low

and the Data Memory. All locations are read/written

except for the data memory which can be read only.

Accesses from the microport to the connection

memory and the data memory are multiplexed with

accesses from the input and output TDM ports. This

can cause variable Data Acknowledge delays (DTA).

Figure 3 - Address Memory Map

Note: "x" Don’t care

Software Control

The address lines on the microprocessor interface

give access to the MT89L85 internal registers and

memories. If the A5,A1,A0 address line inputs are

LOW, then the MT89L85 Internal Control Register is

addressed (see Figure 3). If A5 input line is HIGH,

then the remaining address input lines are used to

select

Memory

subsections

locations

corresponding to the number of channels per input or

output stream. As explained in the Control register

LOCATION

•

Control Register

Channel 0

Channel 1

•

Channel 31

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