TMP112 datasheet(14/33 Pages) TI1

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Frame 1 SMBus ALERT response address byte

Frame 2 slave address from device

Start By

Master

ACK by

device

From

device

NACK by

master

Stop by

master

SDA

SCL

ALERT

R/W

Status

Frame 1 two-wire slave address byte

Frame 2 pointer register byte

Start by

master

ACK by

device

ACK by

device

Frame 3 two-wire slave address byte

Frame 4 data byte 1 read register

Start by

master

ACK by

device

ACK by

master

(2)

From

device

SDA

SCL

R/W

SDA

(Continued)

SCL

(Continued)

SDA

(Continued)

SCL

(Continued)

(1)

R/W

Frame 5 data byte 2 read register

Stop by

master

ACK by

master

(3)

From

device

Stop by

master

TMP112-Q1

SLOS887D – SEPTEMBER 2014 – REVISED DECEMBER 2015

www.ti.com

(1)

The values of A0 and A1 are determined by the ADD0 pin.

(2)

The master must leave the SDA pin high to terminate a single-byte read operation.

(3)

The master must leave the SDA pin high to terminate a two-byte read operation.

Figure 12. Two-Wire Timing Diagram for Read Word Format

(1)

The values of A0 and A1 are determined by the ADD0 pin.

Figure 13. Timing Diagram for SMBus ALERT

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